A 400-MHz S/390 microprocessor

A microprocessor implementing IBM S/390 architecture operates in a 10+2 way system at frequencies up to 411 MHz (2.43 ns). The chip is fabricated in a 0.2-/spl mu/m L/sub eff/ CMOS technology with five layers of metal and tungsten local interconnect. The chip size is 17.35 mm/spl times/17.30 mm with...

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Bibliographic Details
Published in:	IEEE journal of solid-state circuits Vol. 32; no. 11; pp. 1665 - 1675
Main Authors:	Webb, C.F., Anderson, C.J., Sigal, L., Shepard, K.L., Liptay, J.S., Warnock, J.D., Curran, B., Krumm, B.W., Mayo, M.D., Camporese, P.J., Schwarz, E.M., Farrell, M.S., Restle, P.J., Averill, R.M., Slegel, T.J., Houtt, W.V., Chan, Y.H., Wile, B., Nguyen, T.N., Emma, P.G., Beece, D.K., Ching-Te Chuang, Price, C.
Format:	Journal Article
Language:	English
Published:	IEEE 01-11-1997
Subjects:	Circuit synthesis Clocks CMOS technology Frequency Integrated circuit interconnections Microprocessors Phase locked loops Power supplies Power system interconnection Tungsten
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Summary:	A microprocessor implementing IBM S/390 architecture operates in a 10+2 way system at frequencies up to 411 MHz (2.43 ns). The chip is fabricated in a 0.2-/spl mu/m L/sub eff/ CMOS technology with five layers of metal and tungsten local interconnect. The chip size is 17.35 mm/spl times/17.30 mm with about 7.8 million transistors. The power supply is 2.5 V and measured power dissipation at 300 MHz is 37 W. The microprocessor features two instruction units (IUs), two fixed point units (FXUs), two floating point units (FPUs), a buffer control element (BCE) with a unified 64-KB L1 cache, and a register unit (RU). The microprocessor dispatches one instruction per cycle. The dual-instruction, fixed, and floating point units are used to check each other to increase reliability and not for improved performance. A phase-locked-loop (PLL) provides a processor clock that runs at 2/spl times/ the system bus frequency. High-frequency operation was achieved through careful static circuit design and timing optimization, along with limited use of dynamic circuits for highly critical functions, and several different clocking/latching strategies for cycle time reduction. Timing-driven synthesis and placement of the control logic provided the maximum flexibility with minimum turnaround time. Extensive use of self-resetting CMOS (SRCMOS) circuits in the on-chip L1 cache provides a 2.0-ns access time and up to 500 MHz operation.
Bibliography:	ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23
ISSN:	0018-9200 1558-173X
DOI:	10.1109/4.641686