Search Results - "Holman, W. T."

Technology Scaling Comparison of Flip-Flop Heavy-Ion Single-Event Upset Cross Sections by Gaspard, N. J., Jagannathan, S., Diggins, Z. J., King, M. P., Wen, S-J., Wong, R., Loveless, T. D., Lilja, K., Bounasser, M., Reece, T., Witulski, A. F., Holman, W. T., Bhuva, B. L., Massengill, L. W.

“…Heavy-ion experimental results from flip-flops in 180-nm to 28-nm bulk technologies are used to quantify single-event upset trends. The results show that as…”
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Impact of Single-Event Transient Duration and Electrical Delay at Reduced Supply Voltages on SET Mitigation Techniques by Maharrey, J. A., Kauppila, J. S., Harrington, R. C., Nsengiyumva, P., Ball, D. R., Haeffner, T. D., Zhang, E. X., Bhuva, B. L., Holman, W. T., Massengill, L. W.

“…Single-event transients (SETs) in 16-/14-nm bulk fin field effect transistor (finFET) logic chains have been measured using a custom-designed test IC. A…”
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On-Chip Measurement of Single-Event Transients in a 45 nm Silicon-on-Insulator Technology by Loveless, T. D., Kauppila, J. S., Jagannathan, S., Ball, D. R., Rowe, J. D., Gaspard, N. J., Atkinson, N. M., Blaine, R. W., Reece, T. R., Ahlbin, J. R., Haeffner, T. D., Alles, M. L., Holman, W. T., Bhuva, B. L., Massengill, L. W.

“…Direct observation of fast-transient single event signatures often involves considerable uncertainty due to the limitations of monitoring circuitry. A…”
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Single-Event Upset Characterization Across Temperature and Supply Voltage for a 20-nm Bulk Planar CMOS Technology by Kauppila, J. S., Kay, W. H., Haeffner, T. D., Rauch, D. L., Assis, T. R., Mahatme, N. N., Gaspard, N. J., Bhuva, B. L., Alles, M. L., Holman, W. T., Massengill, L. W.

“…Isotropic alpha particle single-event upsets (SEU) in flip-flops are characterized over temperature and voltage supply variations in a 20-nm bulk planar…”
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Single-Event Performance of Sense-Amplifier Based Flip-Flop Design in a 16-nm Bulk FinFET CMOS Process by Jiang, H., Zhang, H., Assis, T. R., Narasimham, B., Bhuva, B. L., Holman, W. T., Massengill, L. W.

“…The increasing need for high-speed logic circuits is causing the conventional flip-flop (FF) designs to migrate to differential FF designs. With the small…”
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Effect of Device Variants in 32 nm and 45 nm SOI on SET Pulse Distributions by Maharrey, J. A., Quinn, R. C., Loveless, T. D., Kauppila, J. S., Jagannathan, S., Atkinson, N. M., Gaspard, N. J., Zhang, E. X., Alles, M. L., Bhuva, B. L., Holman, W. T., Massengill, L. W.

“…Single-Event Transient (SET) pulse widths were obtained from the heavy-ion irradiation of inverters designed in 32 nm and 45 nm silicon-on-insulator (SOI). The…”
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Impact of Process Variations and Charge Sharing on the Single-Event-Upset Response of Flip-Flops by Kauppila, A. V., Bhuva, B. L., Massengill, L. W., Holman, W. T., Ball, D. R.

“…Process variations and charge sharing impact the single-event circuit response. This paper correlates parameter shift impact on the single-event upset (SEU)…”
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A Hardened-by-Design Technique for RF Digital Phase-Locked Loops by Loveless, T.D., Massengill, L.W., Bhuva, B.L., Holman, W.T., Witulski, A.F., Boulghassoul, Y.

“…A RHBD topology for digital phase-locked loops (DPLLs) has been developed for single-event transient (SET) mitigation. By replacing the vulnerable…”
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Sensitivity of High-Frequency RF Circuits to Total Ionizing Dose Degradation by Jagannathan, S., Loveless, T. D., Zhang, E. X., Fleetwood, D. M., Schrimpf, R. D., Haeffner, T. D., Kauppila, J. S., Mahatme, N., Bhuva, B. L., Alles, M. L., Holman, W. T., Witulski, A. F., Massengill, L. W.

“…The combined effects of TID, process corner, and temperature on the performance of high frequency RF circuits are presented. TID experiments at 25°C and 100°C…”
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Impact of Process Variations on SRAM Single Event Upsets by Kauppila, A V, Bhuva, B L, Kauppila, J S, Massengill, L W, Holman, W T

“…Process variations affect the single event (SE) hardness of SRAM cells. Monte-Carlo simulations show this effect and can be used to quantify the significance…”
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Demonstration of a Differential Layout Solution for Improved ASET Tolerance in CMOS A/MS Circuits by Armstrong, S E, Olson, B D, Holman, W T, Warner, J, McMorrow, D, Massengill, L W

“…Layout techniques that exploit charge-sharing phenomena for analog single-event transient (ASET) mitigation in fully-differential analog/mixed-signal (A/MS)…”
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Differential Charge Cancellation (DCC) Layout as an RHBD Technique for Bulk CMOS Differential Circuit Design by Blaine, R. W., Atkinson, N. M., Kauppila, J. S., Armstrong, S. E., Hooten, N. C., Warner, J. H., Holman, W. T., Massengill, L. W.

“…A novel RHBD technique utilizing charge sharing to mitigate single-event voltage transients in differential circuits is demonstrated experimentally…”
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RHBD Bias Circuits Utilizing Sensitive Node Active Charge Cancellation by Blaine, R. W., Armstrong, S. E., Kauppila, J. S., Atkinson, N. M., Olson, B. D., Holman, W. T., Massengill, L. W.

“…A novel radiation-hardened-by-design (RHBD) technique that utilizes charge sharing to mitigate single-event voltage transients is employed to harden bias…”
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Single-Event Analysis and Hardening of Mixed-Signal Circuit Interfaces in High-Speed Communications Devices by Armstrong, S. E., Blaine, R. W., Holman, W. T., Massengill, L. W.

“…High-speed communication systems typically employ a mix of signal types and circuit topologies in order to optimize efficient data propagation. Current-mode…”
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Digital Control for Radiation-Hardened Switching Converters in Space by Adell, P C, Witulski, A F, Schrimpf, R D, Baronti, F, Holman, W T, Galloway, K F

“…Single-event hardening solutions for two converter designs with digital control are considered for space radiation environments: 1) a boost converter using…”
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Single-Event Transient Error Characterization of a Radiation-Hardened by Design 90 nm SerDes Transmitter Driver by Armstrong, S.E., Olson, B.D., Popp, J., Braatz, J., Loveless, T.D., Holman, W.T., McMorrow, D., Massengill, L.W.

“…The analysis and measurement of a radiation hardened by design 3.125 Gbps SerDes transmitter driver fabricated in commercial 90 nm CMOS is presented. The…”
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Radiation Hardened by Design Subsampling Phase-Locked Loop Techniques in PD-SOI by Richards, Ellis W., Loveless, T. D., Kauppila, J. S., Haeffner, T. D., Holman, W. T., Massengill, L. W.

“…This article presents the radiation hardened by design (RHBD) techniques applied to a 15-GHz quadrature subsampling phase-locked loop (PLL) at a sub-50 nm…”
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Modeling Total-Dose Effects for a Low-Dropout Voltage Regulator by Ramachandran, V., Narasimham, B., Fleetwood, D.M., Schrimpf, R.D., Holman, W.T., Witulski, A.F., Pease, R.L., Dunham, G.W., Seiler, J.E., Platteter, D.G.

“…Total ionizing dose effects in a low-dropout voltage regulator are explained based on experimental data and circuit simulations. Transistor gain degradation is…”
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Frequency Dependence of Heavy-Ion-Induced Single-Event Responses of Flip-Flops in a 16-nm Bulk FinFET Technology by Zhang, H., Jiang, H., Bhuva, B. L., Kauppila, J. S., Holman, W. T., Massengill, L. W.

“…Integrated circuits fabricated at advanced technology nodes are expected to operate in gigahertz range of frequencies. At these frequencies, single-event…”
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Dual-Interlocked Logic for Single-Event Transient Mitigation by Maharrey, J. A., Kauppila, J. S., Harrington, R. C., Nsengiyumva, P., Ball, D. R., Haeffner, T. D., Zhang, E. X., Bhuva, B. L., Holman, W. T., Massengill, L. W.

“…A combinational logic family, termed dual-interlocked logic (DIL), designed for single-event transient (SET) mitigation has been fabricated at a 16nm/14nm bulk…”
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