Search Results - "Holleman, Jeremy"
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Programmable Energy-Efficient Analog Multilayer Perceptron Architecture Suitable for Future Expansion to Hardware Accelerators
Published in Journal of low power electronics and applications (01-09-2023)“…A programmable, energy-efficient analog hardware implementation of a multilayer perceptron (MLP) is presented featuring a highly programmable system that…”
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2
On the Impact of Approximate Computation in an Analog DeSTIN Architecture
Published in IEEE transaction on neural networks and learning systems (01-05-2014)“…Deep machine learning (DML) holds the potential to revolutionize machine learning by automating rich feature extraction, which has become the primary…”
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3
A wideband ultra-low-current on-chip ammeter
Published in Proceedings of the IEEE 2012 Custom Integrated Circuits Conference (01-09-2012)“…A high-bandwidth ultra-low-current measurement circuit is presented in this paper. The circuit is capable of measuring an on-chip 75 fA current at a bandwidth…”
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Conference Proceeding -
4
An ultra-low voltage self-startup charge pump for energy harvesting applications
Published in 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) (01-08-2012)“…An ultra-low voltage, self-starting, switched-capacitor based charge pump is proposed for energy harvesting applications. The integrated linear charge pump…”
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Conference Proceeding -
5
A Low-Power High-Precision Comparator With Time-Domain Bulk-Tuned Offset Cancellation
Published in IEEE transactions on circuits and systems. I, Regular papers (01-05-2013)“…A novel time-domain bulk-tuned offset cancellation technique is applied to a low-power high-precision dynamic comparator to reduce its input-referred offset…”
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6
An Ultralow-Power Low-Noise CMOS Biopotential Amplifier for Neural Recording
Published in IEEE transactions on circuits and systems. II, Express briefs (01-10-2015)“…This brief presents a design strategy for a neural recording amplifier array with ultralow-power low-noise operation that is suitable for large-scale…”
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Fast Simulation of Analog Spiking Neural Network with Device Non-Idealites
Published in IEEE transactions on circuits and systems. II, Express briefs (01-09-2023)“…We present a method for spiking neural network simulation with hardware realistic device non-idealities present in the neuron and synapse circuits as an…”
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A Sub-Microwatt Low-Noise Amplifier for Neural Recording
Published in 2007 29th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (01-01-2007)“…In this paper we present a pre-amplifier designed for neural recording applications. Extremely low power dissipation is achieved by operating in an open-loop…”
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Conference Proceeding Journal Article -
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Low Power Compact Analog Spiking Neuron Circuit Using Exponential Positive Feedback With Adaptation and Bursting Capability
Published in 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS) (01-08-2020)“…The authors present an analog spiking neuron design with a small number of transistors operating with a low supply voltage. This is achieved by using the…”
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Conference Proceeding -
10
Hardware Model Based Simulation of Spiking Neuron Using Phase Plane
Published in 2021 IEEE International Symposium on Circuits and Systems (ISCAS) (01-05-2021)“…We present a method to simulate spiking neurons with device nonidealities present in the neuron model. Machine learning algorithms are tested in spiking neural…”
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Conference Proceeding -
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Leakage Current Compensation in Large Number of Inactive Synapses in a 130nm CMOS Process
Published in 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS) (01-08-2020)“…Hardware implementations of neuromorphic circuits have been limited mostly in technology nodes that are much older than more advanced CMOS technology nodes…”
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Conference Proceeding -
12
Design of Ultra-Low Power Biopotential Amplifiers for Biosignal Acquisition Applications
Published in IEEE transactions on biomedical circuits and systems (01-08-2012)“…Rapid development in miniature implantable electronics are expediting advances in neuroscience by allowing observation and control of neural activities. The…”
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13
Spiking Sparse Coding Algorithm with Reduced Inhibitory Feedback Weights
Published in 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS) (01-08-2020)“…In this paper we demonstrate that a sparse coding algorithm using spiking neurons can be designed to have reduced inhibitory feedback connections by modifying…”
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Conference Proceeding -
14
A fast convergent and energy efficient offset calibration technique for dynamic comparators
Published in 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS) (01-08-2017)“…A novel offset calibration technique with fast convergence rate for high-speed dynamic comparators is presented. The circuit utilizes a multi-rate charge pump…”
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Conference Proceeding -
15
Implementation of Linear Discriminant Classifier in 130nm Silicon Process
Published in 2018 IEEE International Symposium on Circuits and Systems (ISCAS) (27-05-2018)“…In this paper, an analog implementation of a linear classifier is analyzed and its performance is measured on a classification task. Noise analysis is done for…”
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Conference Proceeding -
16
A Digital 1.6 pJ/bit Chip Identification Circuit Using Process Variations
Published in IEEE journal of solid-state circuits (01-01-2008)“…A 128-bit, 1.6 pJ/bit, 96% stable chip ID generation circuit utilizing process variations is designed in a 0.13 mum CMOS process. The circuit consumes 162 nW…”
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A 4 I14W dual-modulus frequency divider with 198 % locking range for MICS band applications
Published in Analog integrated circuits and signal processing (01-12-2013)“…This paper presents the design and performance of an ultra-low-power 4/5 frequency divider based on a CMOS ring oscillator. Measurements show a 198 % locking…”
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18
Design considerations for neural amplifiers
Published in 2016 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC) (01-08-2016)“…The initial amplification stage is a critical element of a neural signal acquisition system, and the design of low-noise, low-power amplifiers has received a…”
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Conference Proceeding Journal Article -
19
A 1 TOPS/W Analog Deep Machine-Learning Engine With Floating-Gate Storage in 0.13 µm CMOS
Published in IEEE journal of solid-state circuits (01-01-2015)“…An analog implementation of a deep machine-learning system for efficient feature extraction is presented in this work. It features online unsupervised…”
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20
A 4 μW dual-modulus frequency divider with 198 % locking range for MICS band applications
Published in Analog integrated circuits and signal processing (01-12-2013)“…This paper presents the design and performance of an ultra-low-power 4/5 frequency divider based on a CMOS ring oscillator. Measurements show a 198 % locking…”
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Journal Article