Search Results - "Hokazono, Akira"

Evaluation of two-dimensional strain distribution by STEM/NBD by Uesugi, Fumihiko, Hokazono, Akira, Takeno, Shiro

“…We proposed a strain mapping technique by Nano Beam electron Diffraction (NBD) combined with an energy filter (EF) and a scanning transmission electron…”
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Implementation of TFET SPICE Model for Ultra-Low Power Circuit Analysis by Tanaka, Chika, Adachi, Kanna, Fujimatsu, Motohiko, Hokazono, Akira, Kondo, Yoshiyuki, Kawanaka, Shigeru

“…We proposed a compact model for tunneling field effect transistors (TFETs), which combines BSIM4. Our proposed model for tunneling current is based on a…”
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Mechanism of Contact Resistance Reduction in Nickel Silicide Films by Pt Incorporation by Sonehara, T., Hokazono, A., Akutsu, H., Sasaki, T., Uchida, H., Tomita, M., Kawanaka, S., Inaba, S., Toyoshima, Y.

“…Platinum (Pt) incorporation into nickel silicide (NiSi) films improves silicide characteristics such as lower contact resistance RC at silicide/Si interface…”
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In situ Doped Embedded-SiGe Source/Drain Technique for 32 nm Node p-Channel Metal–Oxide–Semiconductor Field-Effect Transistor by Okamoto, Hiroki, Hokazono, Akira, Adachi, Kanna, Yasutake, Nobuaki, Itokawa, Hiroshi, Okamoto, Shintaro, Kondo, Masaki, Tsujii, Hideji, Ishida, Tatsuya, Aoki, Nobutoshi, Fujiwara, Makoto, Kawanaka, Shigeru, Azuma, Atsushi, Toyoshima, Yoshiaki

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Enhancement/depletion surface channel field effect transistors of diamond and their logic circuits by HOKAZONO, A, KAWARADA, H

“…Using the p-type surface-conductive layer of diamond film, enhancement mode and depletion mode metal-semiconductor field effect transistors were fabricated on…”
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Electrically isolated metal-semiconductor field effect transistors and logic circuits on homoepitaxial diamonds by KAWARADA, H, ITOH, M, HOKAZONO, A

“…Isolated metal-semiconductor field effect transistors (MESFETs) have been fabricated on homoepitaxial diamonds grown by microwave plasma chemical vapor…”
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Technology-Dependent Modeling of MOSFET Parasitic Capacitances for Circuit Simulation by Navarro, Dondee, Tanaka, Chika, Adachi, Kanna, Naito, Takeshi, Tada, Kenshi, Hokazono, Akira

“…Models for parasitic capacitances in the MOSFET overlap region are developed for circuit simulation. In particular, the overlap capacitance…”
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Corrosion of copper and silver plates by volcanic gases by Watanabe, Masamitsu, Hokazono, Akira, Handa, Takao, Ichino, Toshihiro, Kuwaki, Nobuo

“…Corrosion products that had been formed on copper and silver plates exposed in Miyake Island, where suffered a volcanic eruption in 2000, were analyzed by…”
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Facet-Free Si Selective Epitaxial Growth Adaptable to Elevated Source/Drain MOSFETs with Narrow Shallow Trench Isolation by Miyano, Kiyotaka, Mizushima, Ichiro, Hokazono, KazuyaOhuchi, Tsunashima, Yoshitaka

“…A novel selective epitaxial growth (SEG) process that realizes a facet-free elevated source/drain (S/D) is proposed. The key points are the appropriate…”
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Influence of Reactive Ion Etching Applied to Si Substrate on Epitaxial Si Growth and Its Removal by Hayashi, Hisataka, Ohuchi, Kazuya, Miyano, Kiyotaka, Hokazono, Akira, Mizushima, Ichiro, Ohiwa, Tokuhisa

“…The effects of post-etching treatments on Si selective epitaxial growth (SEG) have been studied. In the case of O 2 downflow treatment, SEG Si had dislocations…”
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25-nm Gate Length nMOSFET With Steep Channel Profiles Utilizing Carbon-Doped Silicon Layers (A P-Type Dopant Confinement Layer) by Hokazono, A, Itokawa, H, Kusunoki, N, Mizushima, I, Inaba, S, Kawanaka, S, Toyoshima, Y

“…Steep channel profiles of scaled transistors are a promising approach for advancing transistor generation in bulk complementary metal-oxide-semiconductor…”
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Forward Body Biasing as a Bulk-Si CMOS Technology Scaling Strategy by Hokazono, A., Balasubramanian, S., Ishimaru, K., Ishiuchi, H., Hu, C., Liu, T.-J.K.

“…Forward body biasing is a promising approach for realizing optimum threshold-voltage ( V TH ) scaling in the era when gate dielectric thickness can no longer…”
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Contact resistance reduction of Pt-incorporated NiSi for continuous CMOS scaling ∼ Atomic level analysis of Pt/B/As distribution within silicide films by Sonehara, T., Hokazono, A., Akutsu, H., Sasaki, T., Uchida, H., Tomita, M., Tsujii, H., Kawanaka, S., Inaba, S., Toyoshima, Y.

“…Platinum (Pt)-incorporation into nickel silicide films is the promising approach to reduce the contact resistance (R C ) at silicide/Si interface. Physical…”
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MOSFET design for forward body biasing scheme by Hokazono, A., Balasubramanian, S., Ishimaru, K., Ishiuchi, H., Tsu-Jae King Liu, Chenming Hu

“…Forward body biasing is a solution for continued scaling of bulk-Si CMOS technology. In this letter, the dependence of 30-nm-gate MOSFET performance on body…”
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MOSFET hot-carrier reliability improvement by forward-body bias by Hokazono, A., Balasubramanian, S., Ishimaru, K., Ishiuchi, H., Chenming Hu, Tsu-Jae King Liu

“…Active threshold voltage V/sub TH/ control via well-substrate biasing can be utilized to satisfy International Roadmap for Semiconductors performance and…”
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A study on aggressive proximity of embedded SiGe with comprehensive source drain extension engineering for 32 nm node high-performance pMOSFET technology by Okamoto, Hiroki, Yasutake, Nobuaki, Kusunoki, Naoki, Adachi, Kanna, Itokawa, Hiroshi, Miyano, Kiyotaka, Ishida, Tatsuya, Hokazono, Akira, Kawanaka, Shigeru, Mizushima, Ichiro, Azuma, Atsushi, Toyoshima, Yoshiaki

“…In general, closer proximity of embedded SiGe (eSiGe) source drain (S/D) structure to the channel improves p-channel metal oxide semiconductor field-effect…”
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A study on aggressive proximity of embedded SiGe with comprehensive source drain extension engineering for 32nm node high-performance pMOSFET technology by Okamoto, Hiroki, Yasutake, Nobuaki, Kusunoki, Naoki, Adachi, Kanna, Itokawa, Hiroshi, Miyano, Kiyotaka, Ishida, Tatsuya, Hokazono, Akira, Kawanaka, Shigeru, Mizushima, Ichiro, Azuma, Atsushi, Toyoshima, Yoshiaki

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High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide by Inaba, S., Okano, K., Matsuda, S., Fujiwara, M., Hokazono, A., Adachi, K., Ohuchi, K., Suto, H., Fukui, H., Shimizu, T., Mori, S., Oguma, H., Murakoshi, A., Itani, T., Iinuma, T., Kudo, T., Shibata, H., Taniguchi, S., Takayanagi, M., Azuma, A., Oyamatsu, H., Suguro, K., Katsumata, Y., Toyoshima, Y., Ishiuchi, H.

“…The 35 nm gate length CMOS devices with oxynitride gate dielectric and Ni salicide have been fabricated to study the feasibility of higher performance…”
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Successful enhancement of metal segregation at NiSi/Si junction through pre-amorphization technique by Nishi, Y., Tsuchiya, Y., Kinoshita, A., Hokazono, A., Koga, J.

“…A new technique to enhance the metal segregation at NiSi/Si interface for reducing contact resistance in source/drain electrodes is proposed. It is…”
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SODEL FET: novel channel and source/drain profile engineering schemes by selective Si epitaxial growth technology by Inaba, S., Miyano, K., Nagano, H., Hokazono, A., Ohuchi, K., Mizushima, I., Oyamatsu, H., Tsunashima, Y., Ishimaru, K., Toyoshima, Y., Ishiuchi, H.

“…In this paper, novel channel and source/drain profile engineering schemes are proposed for sub-50-nm bulk CMOS applications. This device, referred to as the…”
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