Search Results - "Hoffmann, T.Y."

On the impact of the Si passivation layer thickness on the NBTI of nanoscaled Si0.45Ge0.55 pMOSFETs by FRANCO, J, KACZER, B, GROESENEKEN, G, TOLEDANO-LUQUE, M, ROUSSEL, Ph. J, HEHENBERGER, P, GRASSER, T, MITARD, J, ENEMAN, G, WITTERS, L, HOFFMANN, T. Y

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Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization by Ragnarsson, L.-A., Li, Z., Tseng, J., Schram, T., Rohr, E., Cho, M.J., Kauerauf, T., Conard, T., Okuno, Y., Parvais, B., Absil, P., Biesemans, S., Hoffmann, T.Y.

“…A novel gate first integration approach enabling ultra low-EOT is demonstrated. HfO 2 based devices with a zero interface layer and optimized gate-electrode is…”
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WITHDRAWN: Molecular beam epitaxial study of InP(0 0 1)/GaSb/Al2O3 gate stack by Merckling, C., Sun, X., Alian, A., Hoffmann, T.Y., Heyns, M., Caymax, M., Dekoster, J.

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Correlation Between the V Adjustment of nMOSFETs With HfSiO Gate Oxide and the Energy Profile of the Bulk Trap Density by Sahhaf, S., Degraeve, R., Srividya, V., Kaczer, B., Gealy, D., Horiguchi, N., Togo, M., Hoffmann, T.Y., Groeseneken, G.

“…The change of the energy profile of the initially present HfSiO defects in nMOSFETs after V th adjustment by As and Ar implantations is investigated. A…”
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On the impact of the Si passivation layer thickness on the NBTI of nanoscaled Si 0.45Ge 0.55 pMOSFETs by Franco, J., Kaczer, B., Toledano-Luque, M., Roussel, Ph. J., Hehenberger, P., Grasser, T., Mitard, J., Eneman, G., Witters, L., Hoffmann, T.Y., Groeseneken, G.

“…The NBTI reliability of nano-scaled Si 0.45Ge 0.55 pFETs was studied as a function of the Si cap thickness. Individual discharge events are visible in the ΔV…”
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On the impact of TiN film thickness variations on the effective work function of poly-Si/TiN/SiO2 and poly-Si/TiN/HfSiON gate stacks by SINGANAMALLA, R, YU, H. Y, POURTOIS, G, FERAIN, I, ANIL, K. G, KUBICEK, S, HOFFMANN, T. Y, JURCZAK, M, BIESEMANS, S, DE MEYER, K

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Electrical Properties of Low- V Metal-Gated n-MOSFETs Using \hbox\hbox/\hbox as Interfacial Layer Between HfLaO High- \kappa Dielectrics and Si Channel by Chang, S.Z., Yu, H.Y., Adelmann, C., Delabie, A., Wang, X.P., Van Elshocht, S., Akheyar, A., Nyns, L., Swerts, J., Aoulaiche, M., Kerner, C., Absil, P., Hoffmann, T.Y., Biesemans, S.

“…In this letter, we report that by employing the La 2 O 3 /SiO x interfacial layer between HfLaO (La = 10%) high- and Si channel, the Ta 2 C metal-gated…”
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Electrical Properties of Low-[Formula Omitted] Metal-Gated n-MOSFETs Using [Formula Omitted] as Interfacial Layer Between HfLaO High-[Formula Omitted] Dielectrics and Si Channel by Chang, S.Z, Yu, H.Y, Adelmann, C, Delabie, A, Wang, X.P, Van Elshocht, S, Akheyar, A, Nyns, L, Swerts, J, Aoulaiche, M, Kerner, C, Absil, P, Hoffmann, T.Y, Biesemans, S

“…In this letter, we report that by employing the La sub(2)O sub(3)/SiO sub(x ) interfacial layer between HfLaO (La = 10%) high- and Si channel, the Ta sub(2)C…”
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On the impact of TiN film thickness variations on the effective work function of poly-Si/TiN/SiO/sub 2/ and poly-Si/TiN/HfSiON gate stacks by Singanamalla, R., Yu, H.Y., Pourtois, G., Ferain, I., Anil, K.G., Kubicek, S., Hoffmann, T.Y., Jurczak, M., Biesemans, S., De Meyer, K.

“…The impact of TiN film thickness variations on the effective work function (WF) of poly-Si/TiN/SiO/sub 2/ and poly-Si/TiN/HfSiON interfaces has been…”
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Low VT metal-gate/high-k nMOSFETs - PBTI dependence and VT Tune-ability on La/Dy-capping layer locations and Laser annealing conditions by Chang, S.Z., Hoffmann, T.Y., Yu, H.Y., Aoulaiche, M., Rohr, E., Adelmann, C., Kaczer, B., Delabie, A., Favia, P., Van Elshocht, S., Kubicek, S., Scharm, T., Witters, T., Ragnarsson, L.A., Wang, X.P., Cho, H.J., Mueller, M., Chiarella, T., Absil, P., Biesemans, S.

“…This paper provides a comprehensive study of the abnormal PBTI behaviors recently observed in La/Dy-capped high-k films in low-V T nMOSFETs. We found that…”
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3D stacked IC demonstration using a through Silicon Via First approach by Van Olmen, J., Mercha, A., Katti, G., Huyghebaert, C., Van Aelst, J., Seppala, E., Zhao Chao, Armini, S., Vaes, J., Teixeira, R.C., Van Cauwenberghe, M., Verdonck, P., Verhemeldonck, K., Jourdain, A., Ruythooren, W., de Potter de ten Broeck, M., Opdebeeck, A., Chiarella, T., Parvais, B., Debusschere, I., Hoffmann, T.Y., De Wachter, B., Dehaene, W., Stucchi, M., Rakowski, M., Soussan, P., Cartuyvels, R., Beyne, E., Biesemans, S., Swinnen, B.

“…We report for the first time the demonstration of 3D integrated circuits obtained by die-to-die stacking using Cu Through Silicon Vias (TSV). The Cu TSV…”
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Parasitic source/drain resistance reduction in n-channel SOI MuGFETs with 15nm wide fins by Dixit, A., Anil, K.G., Collaert, N., Rooyackers, R., Leys, F., Ferain, I., De Keersgieter, A., Hoffmann, T.Y., Loo, R., Goodwin, M., Zimmerman, P., Caymax, M., De Meyer, K., Jurczak, M., Biesemans, S.

“…We report on a set of process improvements leading to parasitic S/D resistance reduction in n-channel MuGFETs with 60 nm tall and 15 nm wide fins. We…”
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Advanced 2D/3D simulations for laser annealed device using an atomistic kinetic Monte Carlo approach and Scanning Spreading Resistance Microscopy (SSRM) by Noda, T., Eyben, P., Vandervorst, W., Vrancken, C., Rosseel, E., Ortolland, C., Clarysse, T., Goossens, J., De Keersgieter, A., Felch, S., Schreutelkamp, R., Absil, P.P., Jurczak, M., De Meyer, K., Biesemans, S., Hoffmann, T.Y.

“…Atomistic modeling and optimized TCAD simulation strategy for Laser-only annealing device are shown. Multiple laser annealing scans are modeled by using…”
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Analysis of As, P Diffusion and Defect Evolution during Sub-millisecond Non-melt Laser Annealing based on an Atomistic Kinetic Monte Carlo Approach by Noda, T., Vandervorst, W., Felch, S., Parihar, V., Cuperus, A., Mcintosh, R., Vrancken, C., Rosseel, E., Bender, H., Van Daele, B., Niwa, M., Umimoto, H., Schreutelkamp, R., Absil, P.P., Jurczak, M., De Meyer, K., Biesemans, S., Hoffmann, T.Y.

“…n-type dopant diffusion during sub-millisecond (ms) non-melt laser annealing (NLA) is investigated through the experiments and atomistic KMC modeling…”
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Single-Metal Dual-Dielectric (SMDD) gate-first CMOS integration towards low VT and high performance by Ragnarsson, L.-A., Schram, T., Rohr, E., Sebaai, F., Kelkar, P., Wada, M., Kauerauf, T., Aoulaiche, M., Cho, M.J., Kubicek, S., Lauwers, A., Hoffmann, T.Y., Absil, P.P., Biesemans, S.

“…This paper overviews integration challenges of low-V T gate-first CMOS featuring one metal gate electrode and one host dielectric with Al 2 O 3 and La 2 O 3…”
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Selective Epitaxial Si/SiGe for VT Shift Adjustment in High k pMOS Devices by Loo, R., Sorada, H., Inoue, A., Byeong Chan Lee, Sangjin Hyun, Lujan, G., Hoffmann, T.Y., Caymax, M.

“…This work discusses the influence of the underlying SiGe on the growth kinetics during the deposition of the Si-cap layer. The importance and feasibility of…”
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NMOS and PMOS Metal Gate Transistors with Junctions Activated by Laser Annealing by Severi, S., Augendre, E., Falepin, A., Kerner, C., Ramos, J., Eyben, P., Vandervost, W., Curatola, C., Felch, S., Nouri, F., Kraus, P., Parihar, V., Noda, T., Schreutelkamp, R., Hoffmann, T.Y., Absil, P., De Meyer, K., Jurczak, M., Biesemans, S.

“…We demonstrate for the first time the integration of metal gate electrode and non-melt laser annealed junctions in both NMOS and PMOS transistors. We report…”
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