Search Results - "Hock-Chun Chin"

Germanium Multiple-Gate Field-Effect Transistors Formed on Germanium-on-Insulator Substrate by Bin Liu, Xiao Gong, Chunlei Zhan, Genquan Han, Hock-Chun Chin, Moh-Lung Ling, Jie Li, Yongdong Liu, Jiangtao Hu, Daval, N., Veytizou, C., Delprat, D., Bich-Yen Nguyen, Yee-Chia Yeo

“…We demonstrate the integration of high performance p-channel Germanium Multiple-Gate Field-Effect Transistors (MuGFETs) on a Germanium-on-Insulator substrate…”
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High-Permittivity Dielectric Stack on Gallium Nitride Formed by Silane Surface Passivation and Metal-Organic Chemical Vapor Deposition by XINKE LIU, CHIN, Hock-Chun, LENG SEOW TAN, YEO, Yee-Chia

“…We report the first demonstration of an in situ surface-passivation technology for a GaN substrate using vacuum anneal (VA) and silane ( SiH 4 ) treatment in a…”
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In Situ Surface Passivation and CMOS-Compatible Palladium-Germanium Contacts for Surface-Channel Gallium Arsenide MOSFETs by Hock-Chun Chin, Ming Zhu, Chih-Hang Tung, Samudra, G.S., Yee-Chia Yeo

“…In this letter, we report a novel n-channel GaAs MOSFET featuring TaN/HfAlO/GaAs gate stack with in situ surface passivation (vacuum anneal and silane…”
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Silane-Ammonia Surface Passivation for Gallium Arsenide Surface-Channel n-MOSFETs by Chin, Hock-Chun, Zhu, Ming, Liu, Xinke, Lee, Hock-Koon, Shi, Luping, Tan, Leng-Seow, Yeo, Yee-Chia

“…A novel surface passivation technology employing silane (SiH 4 ) and ammonia (NH 3 ) was demonstrated to realize high-quality metal-gate/high- k dielectric…”
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Source and Drain Series Resistance Reduction for N-Channel Transistors Using Solid Antimony (Sb) Segregation (SSbS) During Silicidation by Hoong-Shing Wong, Koh, A.T.-Y., Hock-Chun Chin, Lap Chan, Samudra, G., Yee-Chia Yeo

“…We report the first integration of a novel solid antimony (Sb) segregation (SSbS) process in a transistor fabrication flow. A thin solid Sb layer, which acts…”
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Strained-SOI n-Channel Transistor With Silicon-Carbon Source/Drain Regions for Carrier Transport Enhancement by King-Jien Chui, Kah-Wee Ang, Hock-Chun Chin, Chen Shen, Lai-Yin Wong, Chih-Hang Tung, Balasubramanian, N., Ming Fu Li, Samudra, G.S., Yee-Chia Yeo

“…A novel 80 nm gate length strained-Si n-channel transistor structure with lattice-mismatched source and drain (S/D) formed on thin-body silicon-on-insulator…”
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In situ Surface Passivation of Gallium Nitride for Metal-Organic Chemical Vapor Deposition of High-Permittivity Gate Dielectric by XINKE LIU, CHIN, Hock-Chun, TAN, Leng-Seow, YEO, Yee-Chia

“…We report the demonstration of novel techniques for surface passivation of gallium nitride (GaN), comprising the steps of in situ vacuum anneal (VA) and…”
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Carrier Backscattering Characteristics of Strained N-MOSFET Featuring Silicon-Carbon Source/Drain Regions by Kah-Wee Ang, Hock-Chun Chin, King-Jien Chui, Ming-Fu Li, Ganesh Samudra, Yee-Chia Yeo

“…The physics of carrier transport in a sub-90nm strained SOI n-MOSFET with silicon-carbon (SiC) source/drain (S/D) regions is investigated for the first time…”
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Silane and Ammonia Surface Passivation Technology for High-Mobility \hbox\hbox\hbox MOSFETs by Chin, Hock-Chun, Liu, Xinke, Gong, Xiao, Yeo, Yee-Chia

“…We report the integration of silane and ammonia (SiH 4 + NH 3 ) surface passivation technology to realize high-quality gate stack on a high-mobility In 0.53 Ga…”
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Fabrication of gate stack with high gate work function for implantless enhancement-mode GaAs n-channel metal-oxide-semiconductor field effect transistor applications by Zhu, Ming, Chin, Hock-Chun, Samudra, Ganesh S., Yeo, Yee-Chia

“…The guidelines for the selection of gate stacks in using an implantless enhancement-mode GaAs n-channel metal-oxide-semiconductor field effect transistor,…”
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III-V Multiple-Gate Field-Effect Transistors With High-Mobility \hbox\hbox\hbox Channel and Epi-Controlled Retrograde-Doped Fin by Chin, Hock-Chun, Gong, Xiao, Wang, Lanxiang, Lee, Hock Koon, Shi, Luping, Yeo, Yee-Chia

“…We report an In 0.7 Ga 0.3 As n-channel multiple-gate field-effect transistor (MuGFET), featuring a lightly doped high-mobility channel with 70% indium and an…”
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Source/Drain Engineering for In0.7Ga0.3As N-Channel Metal--Oxide--Semiconductor Field-Effect Transistors: Raised Source/Drain with In situ Doping for Series Resistance Reduction by Gong, Xiao, Chin, Hock-Chun, Koh, Shao-Ming, Wang, Lanxiang, Ivana, Zhu, Zhu, Wang, Benzhong, Chia, Ching Kean, Yeo, Yee-Chia

“…In this paper, we report N-channel metal--oxide--semiconductor field-effect transistors (N-MOSFETs) featuring in situ doped raised In 0.53 Ga 0.47 As…”
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Strained In0.53Ga0.47As n-MOSFETs: Performance boost with in-situ doped lattice-mismatched source/drain stressors and interface engineering by Hock-Chun Chin, Xiao Gong, Xinke Liu, Zhe Lin, Yee-Chia Yeo

“…We report the first demonstration of strained III-V n-MOSFETs with lattice-mismatched source/drain (S/D) stressors. Lateral tensile strain was induced by In…”
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Carrier backscattering characteristics of strained silicon-on-insulator n-MOSFETs featuring silicon–carbon source/drain regions by Ang, Kah-Wee, Chin, Hock-Chun, Chui, King-Jien, Li, Ming-Fu, Samudra, Ganesh S., Yeo, Yee-Chia

“…This work investigates for the first time, the physics of carrier transport in a sub-90 nm strained silicon-on-insulator (SOI) n-MOSFET with silicon–carbon…”
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III-V MOSFETs with a new self-aligned contact by Zhang, Xingui, Guo, Huaxin, Ko, Chih-Hsin, Wann, Clement H., Cheng, Chao-Ching, Lin, Hau-Yu, Chin, Hock-Chun, Gong, Xiao, Lim, Phyllis Shi Ya, Luo, Guang-Li, Chang, Chun-Yen, Chien, Chao-Hsin, Han, Zong-You, Huang, Shih-Chiang, Yeo, Yee-Chia

“…We report the first demonstration of III-V n-MOSFETs with self-aligned contact technology. The self-aligned contact was formed using a salicide-like process…”
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A New Salicidation Process with Solid Antimony (Sb) Segregation (SSbS) for Achieving Sub-0.1 eV Effective Schottky Barrier Height and Parasitic Series Resistance Reduction in N-Channel Transistors by Hoong-Shing Wong, Koh, A.T.-Y., Hock-Chun Chin, Lee, R.T.-P., Lap Chan, Samudra, G., Yee-Chia Yeo

“…We report a new CMOS-compatible salicidation process to achieve sub-0.1 eV effective Schottky barrier (SB) height for NiSi/n-Si, one of the lowest values…”
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III―V Multiple-Gate Field-Effect Transistors With High-Mobility In0.7Ga0.3As Channel and Epi-Controlled Retrograde-Doped Fin by CHIN, Hock-Chun, XIAO GONG, LANXIANG WANG, HOCK KOON LEE, LUPING SHI, YEO, Yee-Chia

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Lattice-Mismatched In0.4Ga0.6As Source/Drain Stressors With In Situ Doping for Strained In0.53Ga0.47As Channel n-MOSFETs by CHIN, Hock-Chun, XIAO GONG, XINKE LIU, YEO, Yee-Chia

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Silane and Ammonia Surface Passivation Technology for High-Mobility [Formula Omitted] MOSFETs by Chin, Hock-Chun, Liu, Xinke, Gong, Xiao, Yeo, Yee-Chia

“…We report the integration of silane and ammonia [Formula Omitted] surface passivation technology to realize high-quality gate stack on a high-mobility [Formula…”
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Silane and Ammonia Surface Passivation Technology for High-Mobility hbox In 0.53 hbox Ga 0.47 hbox As MOSFETs by Chin, Hock-Chun, Liu, Xinke, Gong, Xiao, Yeo, Yee-Chia

“…We report the integration of silane and ammonia ( hbox SiH 4 + hbox NH 3 ) surface passivation technology to realize high-quality gate stack on a high-mobility…”
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