Search Results - "Hite, L.R."

Characteristics and three-dimensional integration of MOSFET's in small-grain LPCVD polycrystalline Silicon by Malhi, S.D.S., Shichijo, H., Banerjee, S.K., Sundaresan, R., Elahy, M., Pollack, G.P., Richardson, W.F., Shah, A.H., Hite, L.R., Womack, R.H., Chatterjee, P.K., Lam, H.W.

“…Building on nearly two decades of reported results for MOSFET's fabricated in small-grain polycrystalline silicon, a design methodology is developed that…”
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Characteristics and Three-Dimensional Integration of MOSFET's in Small-Grain LPCVD Polycrystalline Silicon by Malhi, S.D.S., Shichijo, H., Banerjee, S.K., Sundaresan, R., Elahy, M., Pollack, G.P., Richardson, W.F., Shah, A.H., Hite, L.R., Womack, R.H., Chatterjiee, P.K., Hon Wai Lam

“…Building on nearly two decades of reported results for MOSFET's fabricated in small-grain polycrystalline silicon, a design methodology is developed that…”
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Process and performance comparison of an 8K × 8-bit SRAM in three stacked CMOS technologies by Hite, L.R., Sundaresan, R., Malhi, S.D.S., Lam, H.W., Shah, A.H., Hester, R.K., Chatterjee, P.K.

“…Using self-aligned and non-self-aligned stacked CMOS technologies experimental 8K × 8-bit static random-access memories (SRAM'S) have been fabricated. Hydrogen…”
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Time-dependent hole and electron trapping effects in SIMOX buried oxides by Boesch, H.E., Taylor, T.L., Hite, L.R., Bailey, W.E.

“…The back-channel threshold shift associated with the buried oxide layers of separation by implanted oxygen (SIMOX) and zone-melted recrystallization (ZMR)…”
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Model for CMOS/SOI single-event vulnerability by Kerns, S.E., Massengill, L.W., Kerns, D.V., Alles, M.L., Houston, T.W., Lu, H., Hite, L.R.

“…A lumped-parameter model derived from transistor characterization data has been used in SPICE analyses to study and predict the single-event-upset thresholds…”
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An SEU resistant 256 K SOI SRAM by Hite, L.R., Lu, H., Houston, T.W., Hurta, D.S., Bailey, W.E.

“…A novel SEU (single event upset) resistant SRAM (static random access memory) cell has been implemented in a 256 K SOI (silicon on insulator) SRAM that has…”
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Time-dependence hole and electron trapping effects in SIMOX buried oxides by Boesch, H.E. Jr, Taylor, T.L., Hite, L.R., Bailey, W.E.

“…Back-channel threshold shift associated with the buried oxide layers of separation by implanted oxygen (SIMOX) and zone-melted recrystallization (ZMR)…”
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Titanium nitride local interconnect technology for VLSI by Tang, T.E., Che-Chia Wei, Haken, R.A., Holloway, T.C., Hite, L.R., Blake, T.G.W.

“…This paper reports on how the self-aligned titanium disilicide process, normally used to simultaneously reduce MOS gate and junction sheet resistances to less…”
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IIB-1 1.25-µm buried-oxide SOI/CMOS process for 16K/64K SRAMS by Chen, C.-E., Matloubian, M., Mao, B.-Y., Sundaresan, R., Slawinski, C., Lam, H.W., Blake, T.G.W., Hite, L.R., Hester, R.K.

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A general purpose 1024-stage electronically programmable transversal filter by Haken, R.A., Pettengill, R.C., Hite, L.R.

“…The architecture, design, and performance of a filter implemented in CCD/NMOS technology is described. The device features programmability of the reference…”
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Radiation Hardness of a Silicon MESFET 4K x 1 sRAM by Houston, T. W., Hite, L. R., Darley, H. M., Shedd, W. M., Zugich, M. H., Lapierre, D. C.

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Processing and transistor characteristics of a 256 K SRAM fabricated on SIMOX by Bailey, W.E., Lu, H., Blake, T.G.W., Hite, L.R., Mei, P., Hurta, D., Houston, T.W., Pollack, G.P.

“…The authors describe the one-micron CMOS technology for a 256 K SRAM (static random-access memory) on SIMOX (separation by implanted oxygen) which produced…”
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A fully self-aligned stacked CMOS 64K SRAM by Sundaresan, R., Malhi, S.D.S., Hite, L.R., Shah, A.H., Lam, H.W., Chatterjee, P.K.

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A 1 mu m CMOS/SOI 64 K SRAM with 10 nA standby current by Houston, T.W., Lu, H., Mei, P., Blake, T.G.W., Hite, L.R., Sundaresan, R., Matloubiam, M., Bailey, W.E., Liu, J., Peterson, A., Pollack, G.

“…Summary form only given. The successful design and fabrication of a 64 K SRAM on SIMOX material is discussed. The advantage of the small junction area…”
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SOI-CMOS 4K SRAM with high dose oxygen implanted substrate by Chen, C.-E., Blake, T.G.W., Hite, L.R., Malhi, S.D.S., Mao, B.-Y., Lam, H.W.

“…This paper reports on the fabrication of a SOI-CMOS 4K SRAM using the implanted buried oxide SOI technology with a minimum feature size of 2.5 µm. The 4K×1…”
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Polysilicon transistors in VLSI MOS memories by Shichijo, H., Malhi, S.D.S., Richardson, W.F., Pollack, G.P., Shah, A.H., Hite, L.R., Banerjee, S.K., Elahy, M., Sundaresan, R., Womack, R.H., Lam, H.W., Chatterjee, P.K.

“…The recent progress on the use of as-deposited, small grain LPCVD polysilicon transistors in VLSI memories is discussed with the emphasis on their applications…”
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