Search Results - "Hinode, K.."

New Nb multi-layer fabrication process for large-scale SFQ circuits by Nagasawa, S., Satoh, T., Hinode, K., Kitagawa, Y., Hidaka, M., Akaike, H., Fujimaki, A., Takagi, K., Takagi, N., Yoshikawa, N.

“…We investigated the most suitable device structure for large-scale SFQ circuits and propose a new Nb 10-layer device structure that is composed of active…”
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Device Yield in Nb-Nine-Layer Circuit Fabrication Process by Hidaka, M., Nagasawa, S., Hinode, K., Satoh, T.

“…We are investigating device yield in our Nb-nine-layer fabrication process for single-flux-quantum (SFQ) circuits, in which the critical current density of the…”
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Development of advanced Nb process for SFQ circuits by Nagasawa, S., Hinode, K., Satoh, T., Akaike, H., Kitagawa, Y., Hidaka, M.

“…We have been developing a 10-kA/cm 2 advanced Nb process in order to fabricate larger scale and higher speed SFQ circuits with over 100k junctions. We have…”
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Yield Evaluation of 10-kA/cm ^ Nb Multi-Layer Fabrication Process Using Conventional Superconducting RAMs by Nagasawa, S.., Satoh, T.., Hinode, K.., Kitagawa, Y.., Hidaka, M..

“…To achieve larger scale and higher speed single flux quantum (SFQ) circuits, we have been developing a 10-kA/cm 2 Nb multi-layer fabrication process composed…”
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Planarization Process for Fabricating Multi-Layer Nb Integrated Circuits Incorporating Top Active Layer by Satoh, T., Hinode, K., Nagasawa, S., Kitagawa, Y., Hidaka, M., Yoshikawa, N., Akaike, H., Fujimaki, A., Takagi, K., Takagi, N.

“…We have developed an advanced process for fabricating a next-generation multi-layer Nb integrated circuit structure incorporating a top active layer. In this…”
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Fabrication process of planarized multi-layer Nb integrated circuits by Satoh, T., Hinode, K., Akaike, H., Nagasawa, S., Kitagawa, Y., Hidaka, M.

“…To improve the operating speed and density of Nb single-flux-quantum integrated circuits, we developed an advanced fabrication process based on NEC's standard…”
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The Effects of a DC Power Layer in a 10-Nb-Layer Device for SFQ LSIs by Akaike, H., Shigehara, K., Fujimaki, A., Satoh, T., Hinode, K., Nagasawa, S., Hidaka, M.

“…We have evaluated the effects of a DC power (DCP) layer in a 10-Nb-layer device using SQUIDs and large-scale Josephson transmission lines (LS-JTLs). The…”
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Hydrogen-Inclusion-Induced Critical Current Deviation of Nb/AlOx/Nb Josephson Junctions in Superconducting Integrated Circuits by Hinode, K., Satoh, T., Nagasawa, S., Hidaka, M.

“…Josephson junctions with niobium electrodes connected with palladium, which is employed in the bump metallization, have about 20% larger critical current…”
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Characteristics of Nb/AlOx/Nb junctions fabricated in planarized multi-layer Nb SFQ circuits by Satoh, T., Hinode, K., Akaike, H., Nagasawa, S., Kitagawa, Y., Hidaka, M.

“…We developed a fabrication process for planarized multi-layer Nb SFQ circuits. This new process has several new steps for achieving a planarized multi-layer…”
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Effects of a DC-Power Layer Under a Ground Plane in SFQ Circuits by Akaike, H., Fujimaki, A., Satoh, T., Hinode, K., Nagasawa, S., Kitagawa, Y., Hidaka, M.

“…Large-scale SFQ integrated circuits require a large amount of dc-bias current. The magnetic fields induced by the dc-bias currents and the return currents…”
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Inductances of striplines and stacked vias in planarized multi-layer Nb circuits by Akaike, H., Satoh, T., Hinode, K., Nagasawa, S., Kitagawa, Y., Hidaka, M.

“…We have evaluated the inductances of the striplines and the stacked vias which are realized in the planarized 6-Nb-layer device fabricated by our advanced Nb…”
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Resistivity Increase in Ultrafine-Line Copper Conductor for ULSIs by Hinode, Kenji, Hanaoka, Yuko, Takeda, Ken-ichi, Kondo, Seiichi

“…The resistivities of copper (Cu) thin films and damascene Cu fine lines were precisely measured by utilizing Matthiessen's rule. It was shown that this…”
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Effect of photomask pattern shape for a junction counter-electrode on critical current uniformity and controllability in Nb/AlOx/Nb junctions by AKAIKE, H, KITAGAWA, Y, SATOH, T, HINODE, K, NAGASAWA, S, HIDAKA, M

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Improvement of Fabrication Process for 10- ^ Multi-Layer Nb Integrated Circuits by Satoh, T.., Hinode, K.., Nagasawa, S.., Kitagawa, Y.., Hidaka, M..

“…We have developed an advanced fabrication process for fabricating Nb integrated circuits with up to nine planarized Nb layers, and with critical current…”
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Reliability evaluation of Nb 10 kA/cm2 fabrication process for large-scale SFQ circuits by Nagasawa, S., Hinode, K., Satoh, T., Akaike, H., Kitagawa, Y., Hidaka, M.

“…We developed a 10 kA/cm2 Nb fabrication process, whose device structure was composed of six planarized Nb-layers, an Nb/AlOx /Nb junction layer, an Mo resistor…”
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Planarization of Josephson junctions for large-scale integrated Nb SFQ circuits by mechanical polishing by Satoh, Tetsuro, Hinode, K., Akaike, H., Kitagawa, Y., Nagasawa, S., Hidaka, M.

“…Mechanical polishing (MP) is a key technology for fabricating multi-layer, large-scale integrated Nb SFQ circuits. This process, however, could possibly…”
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Nb/AlOx/Nb junctions fabricated using ECR plasma etching by Akaike, H., Kitagawa, Y., Satoh, T., Hinode, K., Nagasawa, S., Hidaka, M.

“…We fabricated Nb/AlOx/Nb junctions using electron cyclotron resonance (ECR) plasma etching. When junctions were fabricated using ECR plasma etching for the…”
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Effect of photomask pattern shape for a junction counter-electrode on critical current uniformity and controllability in Nb/AlO/sub x//Nb junctions by Akaike, H., Kitagawa, Y., Satoh, T., Hinode, K., Nagasawa, S., Hidaka, M.

“…The authors evaluated the effect of photomask pattern shape for a counter-electrode on critical current I/sub c/ uniformity and controllability in Nb/AlOx/Nb…”
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Integrated cryogenic current comparator based on superconductor LSI technology by Urano, C, Maruyama, M, Oe, T, Maezawa, M, Yamada, T, Hidaka, M, Satoh, T, Nagasawa, S, Hinode, K, Kiryu, S, Kaneko, N

“…A new implementation of Sullivan-Dziuba type cryogenic current comparators (CCCs) is proposed. We designed an integrated CCC device consisting of a thin-film…”
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Atomic hydrogen enhanced reflow of copper by Miyake, T., Petek, H., Takeda, K., Hinode, K.

“…A low temperature technique for copper metallization using sputter-reflow process is investigated. Metallization of 0.15–1.5 μm prepatterned trenches at a…”
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