Search Results - "Hinata, J."

High power experiment and heat load evaluation of transmission line for the ECH/CD system in JT-60SA by Kobayashi, T., Yamazaki, H., Hiranai, S., Sawahata, M., Terakado, M., Ishita, K., Hinata, J., Sato, F., Wada, K., Ikeda, R., Shinya, T., Yajima, S., Kajiwara, K., Takahashi, K., Moriyama, S.

“…•High-power test of the waveguide transmission line for the ECH/CD system in JT-60SA.•A transmission line with a pre-load enabled simulation of tokamak…”
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Development of an extruded Mg-Zn-Ca-based alloy: new insight on the role of Mn addition in precipitation by Homma, T., Hinata, J., Kamado, S.

“…An age hardenable Mg-2.5Zn-0.1Ca-0.1Mn (mol%) alloy has been developed. The extruded sample followed by a T5 treatment reveals 290 and 269 MPa of tensile and…”
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Evaluation of transmission efficiency of the ECH/CD transmission lines in integrated commissioning phase on JT-60SA by Yamazaki, H., Kobayashi, T., Takahashi, K., Sawahata, M., Hiranai, S., Toida, N., Sato, F., Hinata, J., Terakado, M., Ishita, K., Ikeda, R., Shinya, T., Yajima, S., Kajiwara, K.

“…•A transmission efficiency of ECH/CD transmission line for JT-60SA was evaluated.•Transmission efficiencies of ∼70 % and 80–85 % were achieved for ∼100 m…”
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Evaluation of a newly developed low reflection dummy load for high power millimeter waves by Yamazaki, H., Kobayashi, T., Hiranai, S., Sawahata, M., Toida, N., Sato, F., Hinata, J., Terakado, M., Ishita, K., Ikeda, R., Shinya, T., Yajima, S., Kajiwara, K.

“…•A low reflection dummy load for high-power millimeter wave has been developed.•The low reflection performance was demonstrated by comparison with conventional…”
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Progress and status of the gyrotron development for the JT-60SA ECH/CD system by Kobayashi, T., Sawahata, M., Terakado, M., Hiranai, S., Ikeda, R., Oda, Y., Wada, K., Hinata, J., Yokokura, K., Hoshino, K., Takahashi, K., Isayama, A., Moriyama, S., Sakamoto, K.

“…High-power, long-pulse operations of a gyrotron for JT-60SA (Super-Advanced) have been carried out at 110 GHz (1 MW/100 s) and 138 GHz (1 MW/100 s). These…”
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Long pulse operation of a dual frequency gyrotron for JT-60SA by Kobayashi, T., Sawahata, M., Terakado, M., Hiranai, S., Wada, K., Sato, Y., Hinata, J., Yokokura, K., Hoshino, K., Kajiwara, K., Oda, Y., Takahashi, K., Ikeda, R., Moriyama, S., Sakamoto, K.

“…Long pulse operation of a dual frequency gyrotron for JT-60SA, which can oscillate both 110 GHz and 138 GHz waves, was started. Oscillations at ~0.4 MW for 2 s…”
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A 1.71-million transistor CMOS CPU chip with a testable cache architecture by Saito, Y., Shimazu, Y., Shimizu, T., Shirai, K., Fujioka, I., Nishiwaki, Y., Hinata, J., Shimotsuma, Y., Sakao, M.

“…A 1.71-million transistor CISC CPU chip for the business computer has been developed. The chip is implemented in a 0.8- mu m CMOS double-polysilicon…”
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The Gmicro/100 32-bit microprocessor by Yoshida, T., Shimisu, T., Mizugaki, S., Hinata, J.

“…A description is given of the Gmicro/100, a 32-b VLSI microprocessor based on the TRON specification. The Gmicro/100 five-stage pipeline, prejump mechanism,…”
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Development of a linear motion antenna for the JT-60SA ECRF system by Moriyama, Shinichi, Kobayashi, Takayuki, Isayama, Akihiko, Hoshino, Katsumichi, Suzuki, Sadaaki, Hiranai, Shinichi, Yokokura, Kenji, Sawahata, Masayuki, Terakado, Masayuki, Hinata, Jun, Wada, Kenji, Sato, Yoshikatsu

“…► Development of an antenna featuring linear motion (LM) concept for long pulse electron cyclotron range of frequency (ECRF) heating and current drive in…”
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A 32-bit superscalar microprocessor with 64-bit processing and high bandwidth DRAM interface by Matsuo, M., Kondo, H., Takata, Y., Kobayashi, S., Satoh, M., Yoshida, T., Saito, Y., Hinata, J.-I.

“…This paper describes a 32-bit CISC superscalar microprocessor designed for high-end embedded applications, such as X-window terminals and printers. To realize…”
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A 32-bit microprocessor with high performance bit-map manipulation instructions by Shimizu, T., Iwata, S., Saito, Y., Yoshida, T., Matsuo, M., Hinata, J., Saito, K.

“…The GMICRO/100, a 32-b microprocessor based on the TRON architecture specification, is described. The GMICRO/100 uses high-level instructions, such as those in…”
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Progress in developments of high-power, long-pulse and multi-frequency ECH/CD system for JT-60SA by Kobayashi, T., Ikeda, R., Oda, Y., Takahashi, K., Shidara, H., Sawahata, M., Terakado, M., Hiranai, S., Sato, F., Wada, K., Hinata, J., Yokokura, K., Hoshino, K., Moriyama, S.

“…A gyrotron and a waveguide transmission line, which were developed for electron cyclotron heating and current drive in JT-60SA, have been tested to evaluated…”
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Dual frequency gyrotron development for JT-60SA by Kobayashi, T., Isayama, A., Sawahata, M., Suzuki, S., Terakado, M., Hiranai, S., Wada, K., Sato, Y., Hinata, J., Yokokura, K., Hoshino, K., Kajiwara, K., Sakamoto, K., Moriyama, S.

“…A new dual frequency (110 GHz and 138 GHz) gyrotron development began for JT-60SA. An output power and efficiency higher than 1 MW and 30% with a peak heat…”
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Progress in transmission component developments for JT-60SA ECRF system by Kobayashi, T., Isayama, A., Hoshino, K., Yokokura, K., Suzuki, S., Hiranai, S., Wada, K., Hinata, J., Takahashi, K., Oda, Y., Sakamoto, K., Moriyama, S.

“…Millimeter wave transmission components for JT-60SA ECRF system (1 MW, 100 s per transmission line at 110 GHz) have been developed and tested in JAEA. Vacuum…”
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A multimedia 32 b RISC microprocessor with 16 Mb DRAM by Shimizu, T., Korematu, J., Satou, M., Kondo, H., Iwata, S., Sawai, K., Okumura, N., Ishimi, K., Nakamoto, Y., Kumanoya, M., Dosaka, K., Yamazaki, A., Ajioka, Y., Tsubota, H., Nunomura, Y., Urabe, T., Hinata, J., Saitoh, K.

“…This 32 b microprocessor with on-chip 2 MB DRAM is for multimedia applications that require a low-power embedded microprocessor and large memory. Using a…”
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Self-checking and recovering microprocessor G100FTS for fault-tolerant systems by Terayama, F., Korematsu, J., Kitamura, F., Hinata, J., Enomoto, T.

“…The architecture and implementation of an application-specific processor, the G100FTS, designed for fault-tolerant systems are described. The G100FTS…”
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A 1.71 M-transistor CMOS CPU chip with a testable cache architecture by Saito, Y., Shimazu, Y., Kobayashi, S., Shimizu, T., Matsuo, M., Ohtsuka, A., Shirai, K., Murata, H., Nishiwaki, Y., Fujioka, I., Nabeta, Y., Kanamoto, H., Hiraoka, S., Suzuki, T., Hinata, J., Shimotsuma, Y.

“…A CISC CPU chip for the business computer is described. It contains an integer unit (IU), a double-precision floating-point unit (FPU), an address generation…”
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A 32-bit superscalar microprocessor G/sub MICRO//400 for embedded systems by Korematsu, J., Ueda, T., Matsuo, M., Tani, K., Okumura, N., Ishimi, K., Yoshida, T., Saito, Y., Hinata, J.

“…This paper describes a 32-bit superscalar microprocessor G/sub MICRO//400, based on the TRON architecture specifications. The G/sub MICRO//400 has a dual…”
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A 32b full custom CPU by Hinata, J., Ohtsuka, A., Kaneko, K., Korematsu, J., Nishida, K., Shimoyama, H., Tomisawa, O., Nishiwaki, Y., Kimura, H.

“…A two-chip 32b VLSI CPU chip set with a cycle time of less than 200ns, using a 1.3μm double-level metal process will be reported. Chip contains 242K…”
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