Search Results - "Hillenius, S.J"

Change of editor-in-chief by Hillenius, S.J.

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Light nitrogen implant for preparing thin-gate oxides by Liu, C.T., Ma, Y., Becerro, J., Nakahara, S., Eaglesham, D.J., Hillenius, S.J.

“…We have implanted nitrogen (N/sup +/) into Si substrates before growing thin thermal oxides, and discovered that light N/sup +/ doses of 5×10/sup 13/-5×10/sup…”
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Effects of oxide interface traps and transient enhanced diffusion on the process modeling of PMOS devices by Vuong, H.-H., Rafferty, C.S., Eshraghi, S.A., Lentz, J.L., Zeitzoff, P.M., Pinto, M.R., Hillenius, S.J.

“…We present a model which simulates the trapping of arsenic and boron dopants at the silicon-silicon dioxide interface, and demonstrate that this model gives…”
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High energy ion implantation for profiled tub formation and impurity gettering in deep submicron CMOS technology by Jacobson, D.C., Kamgar, A., Eaglesham, D.J., Lloyd, E.J., Hillenius, S.J., Poate, J.M.

“…High energy ion implantation has been utilized to fabricate profiled tubs and to create gettering sites in deep submicron CMOS devices in bulk and epitaxial…”
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Self-aligned cobalt disilicide for gate and interconnection and contacts to shallow junctions by Murarka, S.P., Fraser, D.B., Sinha, A.K., Levinstein, H.J., Lloyd, E.J., Liu, R., Williams, D.S., Hillenius, S.J.

“…In this paper we present a new gate and interconnection and contact metallization technology that uses cobalt disilicide for both purposes. Cobalt disilicide,…”
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High-performance salicide shallow-junction CMOS devices for submicrometer VLSI application in twin-tub VI by Lu, C.-Y., Sung, J.J., Kirsch, H.C., Tsai, N.-S., Liu, R., Manocha, A.S., Hillenius, S.J.

“…A 3.3-V CMOS technology with 0.6- mu m design rules in sixth-generation twin-tub CMOS (twin-tub VI) was developed. The major features of the device in this…”
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Process limitation and device design tradeoffs of self-aligned TiSi/sub 2/ junction formation in submicrometer CMOS devices by Lu, C.-Y., Sung, J.J., Liu, R., Tsai, N.-S., Sing, R., Hillenius, S.J., Kirsch, H.C.

“…Submicrometer CMOS transistors require shallow junctions to minimize punchthrough and short-channel effects. Salicide technology is a very attractive…”
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Anomalous C-V characteristics of implanted poly MOS structure in n/sup +//p/sup +/ dual-gate CMOS technology by Lu, C.-Y., Sung, J.M., Kirsch, H.C., Hillenius, S.J., Smith, T.E., Manchanda, L.

“…The C-V characteristics of arsenic-doped polysilicon show a gate-bias dependence of the inversion capacitance and a reduction in the expected value of the…”
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Preventing boron penetration through 25-/spl Aring/ gate oxides with nitrogen implant in the Si substrates by Liu, C.T., Ma, Y., Luftman, H., Hillenius, S.J.

“…For gate oxides thinner than 40 /spl Aring/, conventional schemes of incorporating N in the oxides might become insufficient in stopping B penetration. By…”
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Design and benchmarking of BCPMOS versus SCPMOS for an evolutionary 0.25-/spl mu/m CMOS technology by Vuong, H.-H., Eshraghi, S.A., Rafferty, C.S., Hillenius, S.J., Pinto, M.R., Diodato, P.W., Cong, H.-I., Zeitzoff, P.M.

“…TCAD tools were used to design and benchmark 0.25-/spl mu/m buried-channel PMOS (BCPMOS) versus surface-channel PMOS (SCPMOS), for both device and circuit…”
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Design and benchmarking of BCPMOS versus SCPMOS for an evolutionary 0.25-μm CMOS technology by Vuong, H.-H., Eshraghi, S.A., Rafferty, C.S., Hillenius, S.J., Pinto, M.R., Diodato, P.W., Cong, H.-I., Zeitzoff, P.M.

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Effect of implant damage on the gate oxide thickness by Vuong, H.-H, Bude, J, Baumann, F.H, Evans-Lutterodt, K, Ning, J, Ma, Y, Mcmacken, J, Gossmann, H.-J, Silverman, P, Rafferty, C.S, Hillenius, S.J

“…Large area capacitors were fabricated with doping and oxide thickness representative of an n-MOSFET channel region. Capacitance–voltage ( C– V) measurements on…”
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Gate oxide thinning at the active device/FOX boundary in submicrometer PBL isolation by Kamgar, A., Hillenius, S.J., Baker, R.M., Nakahara, S., Bechtold, P.F.

“…The impact of several poly buffer LOCOS processing parameters on the integrity and defect density (yield) of the gate oxide has been investigated by…”
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Integration of poly buffered LOCOS and gate processing for submicrometer isolation technique by Juengling, W., Hillenius, S.J., Chen, M.L., Fritzinger, L.B.

“…A modified poly buffered LOCOS (PBL) process is described which simplifies processing and provides advantages over conventional PBL and LOCOS processes. The…”
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A 6.75 ns 1616 bit multiplier in single-level-metal CMOS technology by Sharma, R., Lopez, A.D., Michejda, J.A., Hillenius, S.J., Andrews, J.M., Studwell, A.J.

“…A 16*16 bit multiplier integrated circuit fabricated in a CMOS technology having only one level of metallization is described. Microarchitecture for the…”
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Ultra-fast (0.5- mu m) CMOS circuits in fully depleted SOI films by Kamgar, A., Hillenius, S.J., Cong, H.-I.L., Field, R.L., Lindenberger, W.S., Celler, G.K., Trimble, L.E., Sheng, T.T.

“…CMOS dual-modulus, divide by 128/129, prescaler circuits were built in thin Si films on SIMOX (separation by implantation of oxygen) wafers. They operated at…”
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A novel, aerosol-nanocrystal floating-gate device for non-volatile memory applications by De Blauwe, J., Ostraat, M., Green, M.L., Weber, G., Sorsch, T., Kerber, A., Klemens, F., Cirelli, R., Ferry, E., Grazul, J.L., Baumann, F., Kim, Y., Mansfield, W., Bude, J., Lee, J.T.C., Hillenius, S.J., Flagan, R.C., Atwater, H.A.

“…This paper describes the fabrication, and structural and electrical characterization of a new, aerosol-nanocrystal floating-gate FET, aimed at non-volatile…”
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IIIB-3 modified Schottky behavior in shallow p+-n junctions formed by outdiffusion from Cobalt silicide by Lebowitz, J., Liu, R., Hillenius, S.J., Lynch, W.T.

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Multigigahertz CMOS dual-modulus prescaler IC by Cong, H.-I., Andrews, J.M., Boulin, D.M., Fang, S.-C., Hillenius, S.J., Michejda, J.A.

“…A low-power CMOS dual-modulus (divide-by-128/129) prescaler IC is described. The IC has been fabricated with symmetric CMOS technology that optimizes…”
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IIIB-8 UPMOS-A new approach to submicrometer VLSI by Foo, P.D., Liu, R., Lebowitz, J., Orlowsky, K.J., Hillenius, S.J., Lynch, W.T.

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