Automotive High-Speed Interfaces: Future Challenges for System-level HV-ESD Protection and First- Time-Right Design

This paper describes future design challenges of discrete system-level ESD protection (high-voltage, low-capacitance) of automotive high-speed data links such as multi-gigabit ETHERNET and SERDES/video-links. A special focus is put on an in-depth analysis and accurate modeling of the complex ESD beh...

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Bibliographic Details
Published in:	2021 43rd Annual EOS/ESD Symposium (EOS/ESD) Vol. 43; pp. 1 - 10
Main Authors:	Bub, Sergej, Mergens, Markus, Hardock, Andreas, Holland, Steffen, Hilbrink, Ayk
Format:	Conference Proceeding
Language:	English Japanese
Published:	EOS/ESD Association, Inc 26-09-2021
Subjects:	Electrostatic discharges Ethernet Inductance Integrated circuits RF signals Systems simulation
Online Access:	Get full text
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Summary:	This paper describes future design challenges of discrete system-level ESD protection (high-voltage, low-capacitance) of automotive high-speed data links such as multi-gigabit ETHERNET and SERDES/video-links. A special focus is put on an in-depth analysis and accurate modeling of the complex ESD behavior of the Common Mode Choke (CMC). Applied within a System Efficient ESD Design (SEED) simulation concept, this allows a detailed understanding of its multifaceted interaction with modern vs. standard ESD discrete components. As demonstrated for advanced data-link ESD protection requirements, this approach can provide important system optimization steps thus enabling first-time-right ESD-RF co-design.
DOI:	10.23919/EOS/ESD52038.2021.9574746