Search Results - "Higashitani, M"

Perioperative Complications After Aorto-iliac Stenting: Associated Factors and Impact on Follow-up Cardiovascular Prognosis by Iida, O, Soga, Y, Takahara, M, Kawasaki, D, Yamauchi, Y, Suzuki, K, Hirano, K, Koshida, R, Kamoi, D, Tazaki, J, Higashitani, M, Shintani, Y, Yamaoka, T, Okazaki, S, Suematsu, N, Tsuchiya, T, Miyashita, Y, Shinozaki, N, Takahashi, H, Uematsu, M

“…Objectives To investigate factors associated with 30-day perioperative complications (POC) after aorto-iliac (AI) stenting, and to compare follow-up…”
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Particle Swarm Optimization Considering the Concept of Predator-Prey Behavior by Higashitani, M., Ishigame, A., Yasuda, K.

“…Recently, a variety of optimization algorithms has developed as systems get complicated. One of those is called Particle Swarm Optimization (PSO). PSO is an…”
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Short-and long-term clinical impact of intravascular ultrasound-guided endovascular treatment for patients with peripheral artery disease by Kodama, T, Higashitani, M, Ueshima, D, Yamaguchi, T, Fujimoto, Y, Kuwabara, M, Miyazaki, R, Anzai, H, Suzuki, K, Jujo, K, Murata, N

“…Abstract Background Intravascular ultrasound (IVUS) has become a standard procedure in coronary intervention, but it is unclear whether IVUS usage improves…”
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Statins bring the prognostic impact only in peripheral artery disease patients with elevated c-reactive proteins -subanalysis from multicenter registry by Shibahashi, E, Jujo, K, Ueshima, D, Fujimoto, Y, Shimazaki, K, Tanaka, T, Murata, T, Miyazaki, T, Matsumoto, M, Tokuyama, H, Shimura, T, Higashitani, M

“…Abstract Introduction Recent trials demonstrated favorable effects of statins on the clinical prognosis, partly through anti-inflammatory properties, in…”
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Three bits per cell floating gate NAND flash memory technology for 30nm and beyond by Nitta, H., Kamigaichi, T., Arai, F., Futatsuyama, T., Endo, M., Nishihara, N., Murata, T., Takekida, H., Izumi, T., Uchida, K., Maruyama, T., Kawabata, I., Suyama, Y., Sato, A., Ueno, K., Takeshita, H., Joko, Y., Watanabe, S., Liu, Y., Meguro, H., Kajita, A., Ozawa, Y., Takeuchi, Y., Hara, T., Watanabe, T., Sato, S., Tomiie, H., Kanemaru, Y., Shoji, R., Lai, C.H., Nakamichi, M., Owada, K., Ishigaki, T., Hemink, G., Dutta, D., Dong, Y., Chen, C., Liang, G., Higashitani, M., Lutze, J.

“…Three bits per cell NAND Flash Memory Technology for 30 nm and beyond has been successfully developed with floating gate technology. Tight natural V th…”
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2206Prevalence and determinants of complicated grief in bereaved caregivers of patients admitted for cardiovascular diseases by Shinada, K, Kohno, T, Fukuda, K, Higashitani, M, Kawamatsu, N, Kitai, T, Shibata, T, Takei, M, Nochioka, K, Nakazawa, G, Shiomi, H, Miyashita, M, Mizuno, A

“…Abstract Introduction Few studies have examined complicated grief in bereaved caregivers of patients with cardiovascular diseases (CVD), in contrast with…”
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Fusion partner–specific mutation profiles and KRAS mutations as adverse prognostic factors in MLL-rearranged AML by Matsuo, Hidemasa, Yoshida, Kenichi, Nakatani, Kana, Harata, Yutarou, Higashitani, Moe, Ito, Yuri, Kamikubo, Yasuhiko, Shiozawa, Yusuke, Shiraishi, Yuichi, Chiba, Kenichi, Tanaka, Hiroko, Okada, Ai, Nannya, Yasuhito, Takeda, June, Ueno, Hiroo, Kiyokawa, Nobutaka, Tomizawa, Daisuke, Taga, Takashi, Tawa, Akio, Miyano, Satoru, Meggendorfer, Manja, Haferlach, Claudia, Ogawa, Seishi, Adachi, Souichi

“…Mixed-lineage leukemia (MLL) gene rearrangements are among the most frequent chromosomal abnormalities in acute myeloid leukemia (AML). MLL fusion patterns are…”
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A 34 MB/s MLC Write Throughput 16 Gb NAND With All Bit Line Architecture on 56 nm Technology by Cernea, R.-A., Long Pham, Moogat, F., Siu Chan, Binh Le, Yan Li, Shouchang Tsao, Tai-Yuan Tseng, Khanh Nguyen, Li, J., Jayson Hu, Jong Hak Yuh, Hsu, C., Fanglin Zhang, Kamei, T., Nasu, H., Kliza, P., Khin Htoo, Lutze, J., Yingda Dong, Higashitani, M., Junnhui Yang, Hung-Szu Lin, Sakhamuri, V., Li, A., Feng Pan, Yadala, S., Taigor, S., Pradhan, K., Lan, J., James Chan, Abe, T., Fukuda, Y., Mukai, H., Kawakami, K., Liang, C., Ip, T., Shu-Fen Chang, Lakshmipathi, J., Huynh, S., Pantelakis, D., Mofidi, M., Quader, K.

“…A 16 Gb 4-state MLC NAND flash memory augments the sustained program throughput to 34 MB/s by fully exercising all the available cells along a selected word…”
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A 40-ns 64-Mb DRAM with 64-b parallel data bus architecture by Taguchi, M., Tomita, H., Uchida, T., Ohnishi, Y., Sato, K., Ema, T., Higashitani, M., Yabu, T.

“…The authors describe circuit techniques for wide input/output (I/O) data path and high-speed 64-Mb dynamic RAMs (DRAMs). A hierarchical data bus structure…”
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A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate by Yan Li, Seungpil Lee, Yupin Fong, Feng Pan, Tien-Chien Kuo, Jongmin Park, Samaddar, T., Hao Thai Nguyen, Mui, M.L., Htoo, K., Kamei, T., Higashitani, M., Yero, E., Gyuwan Kwon, Kliza, P., Jun Wan, Kaneko, T., Maejima, H., Shiga, H., Hamada, M., Fujita, N., Kanebako, K., Tam, E., Koh, A., Lu, I., Kuo, C.C.-H., Pham, T., Huynh, J., Qui Nguyen, Chibvongodze, H., Watanabe, M., Oowada, K., Shah, G., Woo, B., Gao, R., Chan, J., Lan, J., Hong, P., Liping Peng, Das, D., Ghosh, D., Kalluru, V., Kulkarni, S., Cernea, R.-A., Huynh, S., Pantelakis, D., Chi-Ming Wang, Quader, K.

“…A 16 Gb 8-level NAND flash chip on 56 nm CMOS technology has been fabricated and is being reported for the first time. This is the first 3-bit per cell (X3)…”
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A 151-mm ^ 64-Gb 2 Bit/Cell NAND Flash Memory in 24-nm CMOS Technology by Fukuda, K., Watanabe, Y., Makino, E., Kawakami, K., Sato, J., Takagiwa, T., Kanagawa, N., Shiga, H., Tokiwa, N., Shindo, Y., Ogawa, T., Edahiro, T., Iwai, M., Nagao, O., Musha, J., Minamoto, T., Furuta, Y., Yanagidaira, K., Suzuki, Y., Nakamura, D., Hosomura, Y., Tanaka, R., Komai, H., Muramoto, M., Shikata, G., Yuminaka, A., Sakurai, K., Sakai, M., Hong Ding, Watanabe, M., Kato, Y., Miwa, T., Mak, A., Nakamichi, M., Hemink, G., Lee, D., Higashitani, M., Murphy, B., Bo Lei, Matsunaga, Y., Naruke, K., Hara, T.

“…A 64-Gb MLC (2 bit/cell) NAND flash memory with the highest memory density to date as an MLC flash memory, has been successfully developed. To decrease the…”
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A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOS by Trinh, C., Shibata, N., Nakano, T., Ogawa, M., Sato, J., Takeyama, Y., Isobe, K., Le, B., Moogat, F., Mokhlesi, N., Kozakai, K., Hong, P., Kamei, T., Iwasa, K., Nakai, J., Shimizu, T., Honma, M., Sakai, S., Kawaai, T., Hoshi, S., Yuh, J., Hsu, C., Tseng, T., Li, J., Hu, J., Liu, M., Khalid, S., Chen, J., Watanabe, M., Lin, H., Yang, J., McKay, K., Nguyen, K., Pham, T., Matsuda, Y., Nakamura, K., Kanebako, K., Yoshikawa, S., Igarashi, W., Inoue, A., Takahashi, T., Komatsu, Y., Suzuki, C., Kanazawa, K., Higashitani, M., Lee, S., Murai, T., Lan, J., Huynh, S., Murin, M., Shlick, M., Lasser, M., Cernea, R., Mofidi, M., Schuegraf, K., Quader, K.

“…Today NAND flash memory is used for data and code storage in digital cameras, USB devices, cell phones, camcorders, and solid-state disk drives. To satisfy the…”
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A 146-mm/sup 2/ 8-gb multi-level NAND flash memory with 70-nm CMOS technology by Hara, T., Fukuda, K., Kanazawa, K., Shibata, N., Hosono, K., Maejima, H., Nakagawa, M., Abe, T., Kojima, M., Fujiu, M., Takeuchi, Y., Amemiya, K., Morooka, M., Kamei, T., Nasu, H., Chi-Ming Wang, Sakurai, K., Tokiwa, N., Waki, H., Maruyama, T., Yoshikawa, S., Higashitani, M., Pham, T.D., Yupin Fong, Watanabe, T.

“…An 8-Gb multi-level NAND Flash memory with 4-level programmed cells has been developed successfully. The cost-effective small chip has been fabricated in 70-nm…”
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A novel self-aligned shallow trench isolation cell for 90 nm 4 Gbit NAND flash EEPROMs by Ichige, M., Takeuchi, Y., Sugimae, K., Sato, A., Matsui, M., Kamigaichi, T., Kutsukake, H., Ishibashi, Y., Saito, M., Mori, S., Meguro, H., Miyazaki, S., Miwa, T., Takahashi, S., Iguchi, T., Kawai, N., Tamon, S., Arai, N., Kamata, H., Minami, T., Iizuka, H., Higashitani, M., Pham, T., Hemink, G., Momodomi, M., Shirota, R.

“…Recently, the new memory structures, those FG and AA are completely self aligned, are qualified for 4Gb NAND flash memory in 90 nm technology node. This paper…”
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A 56-nm CMOS 99-mm super(2) 8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput by Takeuchi, K, Kameda, Y, Fujimura, S, Otake, H, Hosono, K, Shiga, H, Watanabe, Y, Futatsuyama, T, Shindo, Y, Kojima, M, Iwai, M, Shirakawa, M, Ichige, M, Hatakeyama, K, Tanaka, S, Kamei, T, Fu, J-Y, Cernea, A, Li, Y, Higashitani, M, Hemink, G, Sato, S, Oowada, K, Lee, S-C, Hayashida, N, Wan, J, Lutze, J, Tsao, S, Mofidi, M, Sakurai, K, Tokiwa, N, Waki, H, Nozawa, Y, Kanazawa, K, Ohshima, S

“…A single 3.3-V only, 8-Gb NAND flash memory with the smallest chip to date, 98.8 mm super(2), has been successfully developed. This is the world's first…”
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A 130.7mm2 2-layer 32Gb ReRAM memory device in 24nm technology by Tz-Yi Liu, Tian Hong Yan, Scheuerlein, R., Yingchang Chen, Lee, J. K., Balakrishnan, G., Yee, G., Zhang, H., Yap, A., Ouyang, J., Sasaki, T., Addepalli, S., Al-Shamma, Ali, Chin-Yu Chen, Gupta, M., Hilton, G., Joshi, S., Kathuria, A., Lai, V., Masiwal, D., Matsumoto, M., Nigam, A., Pai, A., Pakhale, J., Chang Hua Siau, Xiaoxia Wu, Yin, R., Liping Peng, Jang Yong Kang, Huynh, S., Huijuan Wang, Nagel, N., Tanaka, Y., Higashitani, M., Minvielle, T., Gorla, C., Tsukamoto, T., Yamaguchi, T., Okajima, M., Okamura, T., Takase, S., Hara, T., Inoue, H., Fasoli, L., Mofidi, M., Shrivastava, R., Quader, K.

“…ReRAM has been considered as one of the potential technologies for the next-generation nonvolatile memory, given its fast access speed, high reliability, and…”
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A 146-mm super(2) 8-gb multi-level NAND flash memory with 70-nm CMOS technology by Hara, T, Fukuda, K, Kanazawa, K, Shibata, N, Hosono, K, Maejima, H, Nakagawa, M, Abe, T, Kojima, M, Fujiu, M, Takeuchi, Y, Amemiya, K, Morooka, M, Kamei, T, Nasu, H, Wang, Chi-Ming, Sakurai, K, Tokiwa, N, Waki, H, Maruyama, T, Yoshikawa, S, Higashitani, M, Pham, T D, Fong, Yupin, Watanabe, T

“…An 8-Gb multi-level NAND Flash memory with 4-level programmed cells has been developed successfully. The cost-effective small chip has been fabricated in 70-nm…”
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A 146- $hbox mm^2$ 8-Gb Multi-Level NAND Flash Memory With 70-nm CMOS Technology by Hara, T., Fukuda, K., Kanazawa, K., Shibata, N., Hosono, K., Maejima, H., Nakagawa, M., Abe, T., Kojima, M., Fujiu, M., Takeuchi, Y., Amemiya, K., Morooka, M., Kamei, T., Nasu, H., Wang, C.-M., Sakurai, K., Tokiwa, N., Waki, H., Maruyama, T., Yoshikawa, S., Higashitani, M., Pham, T.D., Fong, Y., Watanabe, T.

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A 56-nm CMOS 99-mm2 8-Gb multi-level NAND flash memory with 10-MB/s program throughput by TAKEUCHI, Ken, KAMEDA, Yasushi, IWAI, Makoto, SHIRAKAWA, Masanobu, ICHIGE, Masayuki, HATAKEYAMA, Kazuo, TANAKA, Shinichi, KAMEI, Teruhiko, FU, Jia-Yi, CEMEA, Adi, YAN LI, HIGASHITAM, Masaaki, FUJIMURA, Susumu, HEMINK, Gertjan, SATO, Shinji, OOWADA, Ken, LEE, Shih-Chung, HAYASHIDA, Naoki, JUN WAN, LUTZE, Jeffrey, TSAO, Shouchang, MOFIDI, Mehrdad, SAKURAI, Kiyofumi, OTAKE, Hiroyuki, TOKIWA, Naoya, WAKI, Hiroko, NOZAWA, Yasumitsu, KANAZAWA, Kazuhisa, OHSHIMA, Shigeo, HOSONO, Koji, SHIGA, Hitoshi, WATANABE, Yoshihisa, FUTATSUYAMA, Takuya, SHINDO, Yoshihiko, KOJIMA, Masatsugu

“…[...] noise cancellation circuits and the dual VDD-line scheme realize both a small die size and a fast programming…”
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A 56-nm CMOS 99- }^ 8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput by Takeuchi, K., Kameda, Y., Fujimura, S., Otake, H., Hosono, K., Shiga, H., Watanabe, Y., Futatsuyama, T., Shindo, Y., Kojima, M., Iwai, M., Shirakawa, M., Ichige, M., Hatakeyama, K., Tanaka, S., Kamei, T., Jia-Yi Fu, Cernea, A., Yan Li, Higashitani, M., Hemink, G., Sato, S., Oowada, K., Shih-Chung Lee, Hayashida, N., Jun Wan, Lutze, J., Shouchang Tsao, Mofidi, M., Sakurai, K., Tokiwa, N., Waki, H., Nozawa, Y., Kanazawa, K., Ohshima, S.

“…A single 3.3-V only, 8-Gb NAND flash memory with the smallest chip to date, 98.8 mm 2 , has been successfully developed. This is the world's first integrated…”
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