Design of highly reusable interface for AHB verification module

Bus protocols are critical for the operation of a system as all communications are handled through the bus by following a predetermined structure. An IP is designed to verify if the system follows the specified protocol for seamless communications between multiple blocks in the system. As the proces...

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Bibliographic Details
Published in:	2022 6th International Conference on Devices, Circuits and Systems (ICDCS) pp. 357 - 359
Main Authors:	Mahendra, Vignesh T, Shylu Sam, D.S., Hernisha, A J, Atchaya, A Josephine
Format:	Conference Proceeding
Language:	English
Published:	IEEE 21-04-2022
Subjects:	AMBA AHB Circuits and systems Complexity theory Interfacing IP networks Manuals Protocols UVM Verification Wrapping
Online Access:	Get full text
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Summary:	Bus protocols are critical for the operation of a system as all communications are handled through the bus by following a predetermined structure. An IP is designed to verify if the system follows the specified protocol for seamless communications between multiple blocks in the system. As the process technology decreases the number of sub-blocks in the system also increases thus the verification complexity increases. In Traditional verification architecture, the design under test (DUT) signals are individually connected to the verification environment by binding the interface to the subblocks, signals are encapsulated and simplified to handle. In this work, an AHB verification module is designed by employing the interface binding technique.
ISSN:	2644-1802
DOI:	10.1109/ICDCS54290.2022.9780767