Search Results - "Henkel, Jörg"
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Investigation and validation of labelling loop mediated isothermal amplification (LAMP) products with different nucleotide modifications for various downstream analysis
Published in Scientific reports (03-05-2022)“…Loop mediated isothermal amplification (LAMP) is one of the best known and most popular isothermal amplification methods. It's simplicity and speed make the…”
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Comparison of pre-labelled primers and nucleotides as DNA labelling method for lateral flow detection of Legionella pneumophila amplicons
Published in Scientific reports (29-02-2024)“…Labelling of nucleic acid amplicons during polymerase chain reaction (PCR) or isothermal techniques is possible by using both labelled primers and labelled…”
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Using Cy5-dUTP labelling of RPA-amplicons with downstream microarray analysis for the detection of antibiotic resistance genes
Published in Scientific reports (11-10-2021)“…In this report we describe Cy5-dUTP labelling of recombinase-polymerase-amplification (RPA) products directly during the amplification process for the first…”
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An experimental comparison between primer and nucleotide labelling to produce RPA-amplicons used for multiplex detection of antibiotic resistance genes
Published in Scientific reports (21-09-2023)“…Direct labelling of amplification products using isothermal amplification is currently done most frequently by incorporating previously labelled primer…”
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Adaptive Energy Management for Dynamically Reconfigurable Processors
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-01-2014)“…We present an adaptive energy management system for dynamically reconfigurable processors that chooses an energy-minimizing set of custom instructions (CIs)…”
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RESI: Register-Embedded Self-Immunity for Reliability Enhancement
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-05-2014)“…Technology scaling in the nano-CMOS era has reached a point where coping with the failures produced by soft errors has become one of the key challenges when it…”
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Power efficient and workload balanced tiling for parallelized high efficiency video coding
Published in 2014 IEEE International Conference on Image Processing (ICIP) (01-10-2014)“…The increased workload of the High Efficiency Video Coding (HEVC) and processing of high resolution videos require parallelization of the encoding/decoding…”
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Conference Proceeding -
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From Cloud Down to Things: An Overview of Machine Learning in Internet of Things
Published in IEEE internet of things journal (01-06-2019)“…With the numerous Internet of Things (IoT) devices, the cloud-centric data processing fails to meet the requirement of all IoT applications. The limited…”
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Machine Learning for Power, Energy, and Thermal Management on Multicore Processors: A Survey
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-01-2020)“…Due to the high integration density and roadblock of voltage scaling, modern multicore processors experience higher power densities than previous technology…”
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A low latency generic accuracy configurable adder
Published in 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC) (01-06-2015)“…High performance approximate adders typically comprise of multiple smaller sub-adders, carry prediction units and error correction units. In this paper, we…”
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Conference Proceeding -
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AdaPT: Fast Emulation of Approximate DNN Accelerators in PyTorch
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-06-2023)“…Current state-of-the-art employs approximate multipliers to address the highly increased power demands of deep neural network (DNN) accelerators. However,…”
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Meta-Scanner: Detecting Fault Attacks via Scanning FPGA Designs Metadata
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-11-2024)“…With the rise of the big data, processing in the cloud has become more significant. One method of accelerating applications in the cloud is to use field…”
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13
Mapping on multi/many-core systems: survey of current and emerging trends
Published in 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) (29-05-2013)“…The reliance on multi/many-core systems to satisfy the high performance requirement of complex embedded software applications is increasing. This necessitates…”
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Conference Proceeding -
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Co-Design of Approximate Multilayer Perceptron for Ultra-Resource Constrained Printed Circuits
Published in IEEE transactions on computers (01-09-2023)“…Printed Electronics (PE) exhibits on-demand, extremely low-cost hardware due to its additive manufacturing process, enabling machine learning (ML) applications…”
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Model-to-Circuit Cross-Approximation For Printed Machine Learning Classifiers
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-11-2023)“…Printed electronics (PE) promises on-demand fabrication, low non-recurring engineering costs, and sub-cent fabrication costs. It also allows for high…”
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General Chair's Message
Published in 2023 60th ACM/IEEE Design Automation Conference (DAC) (09-07-2023)Get full text
Conference Proceeding -
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ML-Based Thermal and Cache Contention Alleviation on Clustered Manycores With 3-D HBM
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-11-2024)“…Enabled by the recent advancements in 2.5D/3-D integration and packaging, the integration of clustered manycore processors with high-bandwidth memory (HBM) is…”
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Cache-based Side-Channel Attack Mitigation for Many-core Distributed Systems via Dynamic Task Migration
Published in IEEE transactions on information forensics and security (01-01-2023)“…Side-channel attacks (SCA) are a serious threat to cryptographic systems due to mostly unavoidable information leakage. Cache-based SCAs take advantage of…”
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On the Efficiency of Voltage Overscaling under Temperature and Aging Effects
Published in IEEE transactions on computers (01-11-2019)“…Voltage overscaling has received extensive attention in the last decade as an attractive paradigm for systems in which resulting timing errors and thus a loss…”
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Co-Scheduling on Fused CPU-GPU Architectures With Shared Last Level Caches
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-11-2018)“…Fused CPU-GPU architectures integrate a CPU and general-purpose GPU on a single die. Recent fused architectures even share the last level cache (LLC) between…”
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