Search Results - "Heidel, D.F."

Low-Energy Proton-Induced Single-Event-Upsets in 65 nm Node, Silicon-on-Insulator, Latches and Memory Cells by Rodbell, K.P., Heidel, D.F., Tang, H.H.K., Gordon, M.S., Oldiges, P., Murray, C.E.

“…Experimental data are presented showing that low energy (<2 MeV) proton irradiation can upset exploratory 65 nm node, silicon-on-insulator circuits. Alpha…”
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Low Energy Proton Single-Event-Upset Test Results on 65 nm SOI SRAM by Heidel, D.F., Marshall, P.W., LaBel, K.A., Schwank, J.R., Rodbell, K.P., Hakey, M.C., Berg, M.D., Dodd, P.E., Friendlich, M.R., Phan, A.D., Seidleck, C.M., Shaneyfelt, M.R., Xapsos, M.A.

“…Experimental results are presented on proton induced single-event-upsets (SEU) on a 65 nm silicon-on-insulator (SOI) SRAM. The low energy proton SEU results…”
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Alpha-Particle, Carbon-Ion and Proton- Induced Flip-Flop Single-Event-Upsets in 65 nm Bulk Technology by Wissel, L., Cannon, E.H., Heidel, D.F., Gordon, M.S., Rodbell, K.P.

“…This paper presents upset rates of flip-flops in 65 nm commercial bulk technology predicted through modeling, and compares the predictions to upset rates…”
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Latch Design Techniques for Mitigating Single Event Upsets in 65 nm SOI Device Technology by KleinOsowski, A.J., Cannon, E.H., Gordon, M.S., Heidel, D.F., Oldiges, P., Plettner, C., Rodbell, K.P., Rose, R.D., Tang, H.H.K.

“…This paper describes techniques for mitigating single event upsets in master-slave flip-flop latches in 65 nm SOI device technology. Techniques are explained,…”
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An Evaluation of An Ultralow Background Alpha-Particle Detector by Gordon, M.S., Heidel, D.F., Rodbell, K.P., Dwyer-McNally, B., Warburton, W.K.

“…XIA has provided IBM with a prototype ultralow background alpha particle counter for evaluation. Results show a significant decrease in background compared to…”
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Single-Event Upsets and Multiple-Bit Upsets on a 45 nm SOI SRAM by Heidel, D.F., Marshall, P.W., Pellish, J.A., Rodbell, K.P., LaBel, K.A., Schwank, J.R., Rauch, S.E., Hakey, M.C., Berg, M.D., Castaneda, C.M., Dodd, P.E., Friendlich, M.R., Phan, A.D., Seidleck, C.M., Shaneyfelt, M.R., Xapsos, M.A.

“…Experimental results are presented on single-bit-upsets (SBU) and multiple-bit-upsets (MBU) on a 45 nm SOI SRAM. The accelerated testing results show the…”
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Flip-Flop Upsets From Single-Event-Transients in 65 nm Clock Circuits by Wissel, L., Heidel, D.F., Gordon, M.S., Rodbell, K.P., Stawiasz, K., Cannon, E.H.

“…This paper describes upsets of 65 nm flip-flops caused by Single-Event-Transients in clock-tree circuits. The upset rate is predicted through modeling, and…”
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Single-Event-Upset Critical Charge Measurements and Modeling of 65 nm Silicon-on-Insulator Latches and Memory Cells by Heidel, D.F., Rodbell, K.P., Oldiges, P., Gordon, M.S., Tang, H.H.K., Cannon, E.H., Plettner, C.

“…Experimental and modeling results are presented on the critical charge required to upset exploratory 65 nm silicon-on-insulator (SOI) circuits. Using a…”
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Modeling of Alpha-Induced Single Event Upsets for 45 nm Node SOI Devices Using Realistic C4 and 3D Circuit Geometries by Tang, H.H.K., Murray, C.E., Fiorenza, G., Rodbell, K.P., Heidel, D.F.

“…Novel techniques have been applied to model realistic alpha particle source distributions in complex back-end-of-the-line geometries. Rigorous Monte Carlo…”
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An on-chip jitter measurement circuit with sub-picosecond resolution by Jenkins, K.A., Jose, A.P., Heidel, D.F.

“…A circuit for accurate on-chip measurement of timing jitter is demonstrated. Measurements with the circuit show excellent reproduction of corresponding…”
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Multi-bit upsets in 65nm SOI SRAMs by Cannon, E.H., Gordon, M.S., Heidel, D.F., KleinOsowski, A.J., Oldiges, P., Rodbell, K.P., Tang, H.

“…We study multi-bit upsets (MBU) in 65 nm SOI SRAMs. Proton beam and thorium foil experiments demonstrate that SOI SRAMs have lower soft error rate than bulk…”
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Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability by Wei Hwang, Gristede, G., Sanda, P., Wang, S.Y., Heidel, D.F.

“…This paper presents a fast, low-power, binary carry-lookahead, 64-bit dynamic parallel adder architecture for high-frequency microprocessors. The adder core is…”
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Protecting Big Blue from Rogue Subatomic Particles by Cannon, E.H., KleinOsowski, A., Gordon, M.S., Heidel, D.F., Hergenrother, J., Muller, K.P., Oldiges, P., Plettner, C., Reinhardt, D.D., Rodbell, K.P., Tang, H.H.K.

“…Device technology scaling continues to deliver faster and smaller transistors, contributing to IBMs continued leadership in server systems. However, there is…”
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Ion microbeam probing of sense amplifiers to analyze single event upsets in a CMOS DRAM by Geppert, L.M., Bapst, U., Heidel, D.F., Jenkins, K.A.

“…An ion microbeam radiation system has been used to probe the relative contribution of individual circuits and nodes of a CMOS DRAM to single event upsets…”
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Ion microbeam radiation system by Heidel, D.F., Bapst, U.H., Jenkins, K.A., Geppert, L.M., Zabel, T.H.

“…An ion microbeam radiation test system has been built for studying radiation-induced charge collection and single event upsets in advanced semiconductor…”
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A 12-ns low-temperature DRAM by Henkels, W.H., Lu, N.C.C., Hwang, W., Rajeevakumar, T.V., Franch, R.L., Jenkins, K.A., Bucelot, T.J., Heidel, D.F., Immediato, M.J.

“…A 12-ns access-time 0.5-Mb CMOS DRAM (dynamic random-access memory) operated at liquid-nitrogen temperatures is discussed. Comprehensive measurements,…”
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Design and implementation of high performance dynamic 64-bit parallel adder with enhanced testability by Hwang, W., Gristede, G.D., Sanda, P.N., Wang, S.Y., Heidel, D.F.

“…This paper presents a fast, low power, binary carry look-ahead 64-bit dynamic parallel adder architecture for a high frequency microprocessor. The adder core…”
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Thermoelectric charge imbalance in superconducting aluminum by Heidel, D. F., Garland, J. C.

“…The charge imbalance voltage produced in superconducting Al by the presence of a temperature gradient and an electric current has been studied over the range…”
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Submicron CMOS gate electrode discontinuity: electrical signature and effect on circuit speed by Jenkins, K.A., Burghartz, J.N., Agnello, P.D., Heidel, D.F., Wong, C.Y.

“…The importance of vertical continuity of the gate electrodes of submicron CMOS circuits is discussed. A high frequency technique for assessing this continuity…”
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Low temperature SER and noise in a high speed DRAM by Henkels, W.H., Lu, N.C.C., Hwang, W., Rajeevakumar, T.V., Franch, R.L., Jenkins, K.A., Bucelot, T.J., Heidel, D.F., Immediato, M.J.

“…The soft error rate (SER) and power bus noise were measured for a high-speed 512 kb CMOS DRAM (dynamic random access memory) operated at liquid-nitrogen…”
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