Search Results - "Hearne, Kay"

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  1. 1
    A 0.5-16.3 Gbps Multi-Standard Serial Transceiver With 219 mW/Channel in 16-nm FinFET

    A 0.5-16.3 Gbps Multi-Standard Serial Transceiver With 219 mW/Channel in 16-nm FinFET by Erett, Marc, Hudner, James, Carey, Declan, Casey, Ronan, Geary, Kevin, Hearne, Kay, Neto, Pedro, Mallard, Thomas, Sooden, Vikas, Smyth, Mark, Frans, Yohan, Im, Jay, Upadhyaya, Parag, Wenfeng Zhang, Winson Lin, Xu, Bruce, Chang, Ken

    Published in IEEE journal of solid-state circuits (01-07-2017)
    “…This paper presents a flexible-reach 0.5-16.3 Gb/s serial transceiver which is integrated into a field-programmable gate array (FPGA) and fabricated in 16-nm…”
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  2. 2
    A 112-134-Gb/s PAM4 Receiver Using a 36-Way Dual-Comparator TI-SAR ADC in 7-nm FinFET

    A 112-134-Gb/s PAM4 Receiver Using a 36-Way Dual-Comparator TI-SAR ADC in 7-nm FinFET by de Abreu Farias Neto, Pedro Wilson, Hearne, Kay, Chlis, Ilias, Carey, Declan, Casey, Ronan, Griffin, Ben, Ngankem Ngankem, Frantz Stephane F., Hudner, James, Geary, Kevin, Erett, Marc, Laraba, Asma, Eachempatti, Haritha, Kim, Jae Wook, Zhang, Hongtao, Asuncion, Santiago, Frans, Yohan

    Published in IEEE solid-state circuits letters (2020)
    “…This letter describes a 112-134-Gb/s PAM-4 wireline receiver (Rx) designed and fabricated in 7-nm CMOS FinFET technology. The Rx includes a T-Coil-assisted…”
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  3. 3
    A 0.5-16.3Gbps multi-standard serial transceiver with 219mW/channel in 16nm FinFET

    A 0.5-16.3Gbps multi-standard serial transceiver with 219mW/channel in 16nm FinFET by Erett, Marc, Hudner, James, Carey, Declan, Casey, Ronan, Geary, Kevin, Hearne, Kay, Neto, Pedro, Mallard, Thomas, Sooden, Vikas, Smyth, Mark, Frans, Yohan, Im, Jay, Upadhyaya, Parag, Wenfeng Zhang, Winson Lin, Xu, Bruce, Chang, Ken

    “…This paper presents a flexible 0.5-16.3Gb/s serial transceiver - fabricated in 16nm FinFET CMOS - and consuming 219mW/channel at 16.3Gb/s. The transceiver is…”
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  4. 4
    A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET

    A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET by Hudner, James, Carey, Declan, Casey, Ronan, Hearne, Kay, de Abreu Farias Neto, Pedro Wilson, Chlis, Ilias, Erett, Marc, Chi Fung Poon, Laraba, Asma, Hongtao Zhang, Chaitanya Ambatipudi, Sai Lalith, Mahashin, David, Upadhyaya, Parag, Frans, Yohan, Chang, Ken

    Published in 2018 IEEE Symposium on VLSI Circuits (01-06-2018)
    “…A 112Gb/s PAM4 wireline receiver testchip is implemented in 16nm FinFET. The receiver consists of continuous-time linear equalizers, a peaking capacitance…”
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