Search Results - "Hazucha, P."

Impact of CMOS technology scaling on the atmospheric neutron soft error rate by Hazucha, P., Svensson, C.

“…We investigated scaling of the atmospheric neutron soft error rate (SER) which affects reliability of CMOS circuits at ground level and airplane flight…”
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Characterization of soft errors caused by single event upsets in CMOS processes by Karnik, T., Hazucha, P.

“…Radiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in high-performance microprocessors in…”
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Area-efficient linear regulator with ultra-fast load regulation by Hazucha, P., Karnik, T., Bloechel, B.A., Parsons, C., Finan, D., Borkar, S.

“…We demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology. Ultra-fast single-stage load…”
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A Delay-Locked Loop Synchronization Scheme for High-Frequency Multiphase Hysteretic DC-DC Converters by Pengfei Li, Lin Xue, Hazucha, P., Karnik, T., Bashirullah, R.

“…This paper reports a delay-locked loop (DLL) based hysteretic controller for high-frequency multiphase dc-dc buck converters. The DLL control loop employs the…”
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A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package by Hazucha, P., Schrom, G., Jaehong Hahn, Bloechel, B.A., Hack, P., Dermer, G.E., Narendra, S., Gardner, D., Karnik, T., De, V., Borkar, S.

“…We demonstrate an integrated buck dc-dc converter for multi-V/sub CC/ microprocessors. At nominal conditions, the converter produces a 0.9-V output from a…”
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Integrated On-Chip Inductors With Magnetic Films by Gardner, D.S., Schrom, G., Hazucha, P., Paillet, F., Karnik, T., Borkar, S.

“…On-chip inductors with 2 levels of magnetic material were integrated into an advanced 130-nm CMOS process to obtain over an order of magnitude increase in…”
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High-voltage power delivery through charge recycling by Rajapandian, S., Shepard, K.L., Hazucha, P., Karnik, T.

“…In this paper, we describe a technique for delivering power to a digital integrated circuit at high voltages, reducing current demands and easing requirements…”
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High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters by Hazucha, P., Sung Tae Moon, Schrom, G., Paillet, F., Gardner, D., Rajapandian, S., Karnik, T.

“…Integrated DC-DC converters switching above 100MHz dramatically reduce the footprint of the inductors and capacitors while improving droop response…”
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A Band-Limited Active Damping Circuit With 13 dB Power Supply Resonance Reduction by Jianping Xu, Hazucha, P., Zuoguo Wu, Aseron, P., Mingwei Huang, Paillet, F., Schrom, G., Tschanz, J., De, V., Karnik, T., Taylor, G.

“…The impedance of a microprocessor power-delivery network peaks at ~140 MHz, resulting in power-grid resonance, which lowers operating frequency and compromises…”
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Optimized test circuits for SER characterization of a manufacturing process by Hazucha, P., Svensson, C.

“…Novel test circuits for the accurate determination of soft error rate (SER) dependency on critical charges Q/sub CRIT/ have been developed. The minimum charge…”
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Measurements and analysis of SER-tolerant latch in a 90-nm dual-V sub(T) CMOS process by Hazucha, P, Karnik, T, Walstra, S, Bloechel, BA, Tschanz, J W, Maiz, J, Soumyanath, K, Dermer, GE, Narendra, S, De, V, Borkar, S

“…We designed a soft error rate (SER) tolerant latch utilizing local redundancy. We implemented a test chip containing both the standard and SER-tolerant latches…”
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Cosmic-ray soft error rate characterization of a standard 0.6-/spl mu/m CMOS process by Hazucha, P., Svensson, C., Wender, S.A.

“…Cosmic-ray soft errors from ground level to aircraft flight altitudes are caused mainly by neutrons. We derived an empirical model for estimation of soft error…”
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Neutron induced soft errors in CMOS memories under reduced bias by Hazucha, P., Johansson, K., Svensson, C.

“…A custom designed 16 kbit CMOS memory was irradiated by 14 MeV neutrons and 100 MeV neutrons. SEU cross sections were evaluated under different supply…”
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High-frequency DC-DC conversion : fact or fiction by Karnik, T., Hazucha, P., Schrom, G., Paillet, F., Gardner, D.

“…Rapidly increasing input current of microprocessors results in rising cost and motherboard real estate occupied by power delivery system. We show that a…”
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A 100MHz Eight-Phase Buck Converter Delivering 12A in 25mm2 Using Air-Core Inductors by Schrom, G., Hazucha, P., Paillet, F., Rennie, D. J., Moon, S. T., Gardner, D. S., Kamik, T., Sun, P., Nguyen, T. T., Hill, M. J., Radhakrishnan, K., Memioglu, T.

“…We present a 100MHz eight-phase synchronous buck converter using air-core inductors. The voltage regulator (VR) chip was manufactured in a 90nm CMOS process…”
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A 480-MHz, multi-phase interleaved buck DC-DC converter with hysteretic control by Schrom, G., Hazucha, P., Hahn, J., Gardner, D.S., Bloechel, B.A., Dermer, G., Narendra, S.G., Karnik, T., De, V.

“…We propose an on-chip 1.8 V-to-0.9 V DC-DC converter aimed to reduce the input current and decoupling requirements of future microprocessors. By utilizing a…”
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Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/T/ CMOS process by Hazucha, P, Karnik, T, Walstra, S, Bloechel, B A, Tschanz, J W, Maiz, J, Soumyanath, K, Dermer, G E, Narendra, S, De, V, Borkar, S

“…We designed a soft error rate (SER) tolerant latch utilizing local redundancy. We implemented a test chip containing both the standard and SER-tolerant latches…”
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Cosmic-ray soft error rate characterization of a standard 0.6- mu m CMOS process by Hazucha, P, Svensson, C, Wender, SA

“…Cosmic-ray soft errors from ground level to aircraft flight altitudes are caused mainly by neutrons. We derived an empirical model for estimation of soft error…”
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Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation by Schrom, Gerhard, Hazucha, Peter, Hahn, Jae-Hong, Kursun, Volkan, Gardner, Donald, Narendra, Siva, Karnik, Tanay, De, Vivek

“…Rapidly increasing input current of microprocessors resulted in rising cost and motherboard real estate occupied by decoupling capacitors and power routing. We…”
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Selective node engineering for chip-level soft error rate improvement [in CMOS] by Karnik, T., Vangal, S., Veeramachaneni, V., Hazucha, P., Erraguntla, V., Borkar, S.

“…This paper presents a technique to selectively engineer sequential or domino nodes in high performance circuits to improve soft error rate (SER) induced by…”
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