Search Results - "Haw-Jyh Liaw"

Signal integrity issues at split ground and power planes by Haw-Jyh Liaw, Merkelo, H.

“…The signal integrity issues at split ground and power planes are studied by 3D, time-domain, full-wave simulations and SPICE circuit simulations. Dynamics of…”
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A 2.6-GByte/s multipurpose chip-to-chip interface by Lau, B., Yiu-Fai Chan, Moncayo, A., Ho, J., Allen, M., Salmon, J., Liu, J., Muthal, M., Lee, C., Nguyen, T., Horine, B., Leddige, M., Kuojim Huang, Wei, J., Leung Yu, Tarver, R., Yuwen Hsia, Vu, R., Tsern, F., Haw-Jyh Liaw, Hudson, J., Nguyen, D., Donnelly, K., Crisp, R.

“…A 2.6 GByte/s megacell that interfaces to single or double byte wide DRAMs or logic chips is implemented using 0.35-0.18 /spl mu/m CMOS technologies. Special…”
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An 800mW 10Gb ethernet transceiver in 0.13μm CMOS by STEFANOS, Sidiropoulos, NIKHIL, Acharya, AZMEER, Salleh, SIDDHARTH, Sheth, LARS, Thon, KATELIJN, Vleugels, PATRICK, Yue, DON, Stark, PAK, Chau, JOSEPH, Dao, ARNOLD, Felman, HAW-JYH, Liaw, MARC, Loinaz, R, Sekhar Narayanaswami, CLEMENZ, Portmann, SHAHRIAR, Rabii

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An 800 mW 10 Gb Ethernet transceiver in 0.13 /spl mu/m CMOS by Sidiropoulos, S., Acharya, N., Pak Chau, Dao, J., Feldman, A., Haw-Jyh Liaw, Loinaz, M., Narayanaswami, R.S., Portmann, C., Rabii, S., Salleh, A., Sheth, S., Thon, L., Vleugels, K., Yue, P., Stark, D.

“…A fully integrated 10 Gb Ethernet transceiver IC using a standard 0.13 /spl mu/m CMOS process integrates 10.3 Gb/s and 4/spl times/3.12 Gb/s analog front-ends,…”
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Characterization and modeling of multilayer interconnections for high-speed digital systems by Liaw, Haw-Jyh

“…The frequency-dependent characteristics of lossy interconnections such as on-chip metallization and wiring in multichip modules are characterized rigorously by…”
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Crossing the planes at high speed by Liaw, Haw-Jyh, Merkelo, Henri

“…A specific design situation that represents a broad class of problems in the study of signal integrity in computer circuitry is discussed. The effects on…”
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Crossing the planes at high speed. Signal integrity issues at split ground and power planes by Liaw, H.-J., Merkelo, H.

“…This article discusses a specific design situation that represents quite a broad class of problems in the study of signal integrity. The article focuses on the…”
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Simulation and modeling of mode conversion at vias in multilayer interconnections by Liaw, H.-I., Merkelo, H.

“…The process of signal flow at vias in multilayer interconnections is discussed as a general phenomenon involving partial conversion of signal-line waveguide…”
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Interconnect characterization and design optimization for high speed digital applications by Sarfaraz, A., Yuan, C., Haw-Jyh Liaw, Gong-Jong Yeh, Kollipara, R.

“…Interconnect plays a key role in determining the performance of high speed digital systems such as the direct Rambus/sup (R)/ DRAM (RDRAM/sup (R)/) channel,…”
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Physical layer design of a 1.6 GB/s DRAM bus by Moncayo, A., Hindi, S., Ching-Chao Huang, Kollipara, R., Haw-Jyh Liaw, Nguyen, D., Perino, D., Sarfaraz, A., Yuan, C., Leddige, M., McCall, J., Xang Moua, Salmon, J.

“…This paper describes an innovative design and modeling methodology for development of a high performance memory bus with data signaling bandwidth of up to 1.6…”
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