Search Results - "Harmanani, Haidar M"

An outcome-based assessment process for accrediting computing programmes by Harmanani, Haidar M.

“…The calls for accountability in higher education have made outcome-based assessment a key accreditation component. Accreditation remains a well-regarded seal…”
Get full text

A single switcher combined series parallel hybrid envelope tracking amplifier for wideband RF power amplifier applications by Anabtawi, Nijad, Ferzli, Rony, Harmanani, Haidar M.

“…In this paper, an improved architecture for RF power amplifier envelope tracking supply modulator is presented. It consists of a single switched mode supply…”
Get full text

Thermal-aware test scheduling using network-on-chip under multiple clock rates by Salamy, Hassan, Harmanani, Haidar M.

“…The increasing trend in the number of cores on a single chip has led to scalability and bandwidth issues in bus-based communication. Network-on-chip (NoC)…”
Get full text

An enhanced light-load efficiency step down regulator with fine step frequency scaling by Anabtawi, Nijad, Ferzli, Rony, Harmanani, Haidar M.

“…This paper presents a switching DC-DC Buck converter with enhanced light-load efficiency for use in noise-sensitive applications. Low noise, spur free…”
Get full text

An all-digital fast tracking switching converter with a programmable order loop controller for envelope tracking RF power amplifiers by Anabtawi, Nijad, Ferzli, Rony, Harmanani, Haidar M.

“…This paper presents a step down, switched mode power converter for use in multi-standard envelope tracking radio frequency power amplifiers (RFPA). The…”
Get full text

A Stochastic Chartist–Fundamentalist Model with Time Delays by Dibeh, Ghassan, Harmanani, Haidar M.

“…A stochastic chartist–fundamentalist model of speculative asset dynamics in financial markets is developed. The model is represented by a stochastic…”
Get full text

Test bus assignment, sizing, and partitioning for system-on-chip by Harmanani, Haidar M., Sawan, Rachel

“…The test access mechanism (TAM) is an important element of test architectures for embedded cores and is responsible for on-chip test pattern transport from the…”
Get full text

Option pricing during post-crash relaxation times by Dibeh, Ghassan, Harmanani, Haidar M.

“…This paper presents a model for option pricing in markets that experience financial crashes. The stochastic differential equation (SDE) of stock price dynamics…”
Get full text

A Stochastic ChartistDSFundamentalist Model with Time Delays by Dibeh, Ghassan, Harmanani, Haidar M

“…A stochastic chartistDSfundamentalist model of speculative asset dynamics in financial markets is developed. The model is represented by a stochastic…”
Get full text

Integrated test scheduling, wrapper design, and TAM assignment for hierarchical SOC by Harmanani, H.M., Farah, R.

“…System-on-chip (SOCs) test minimization has received a lot of attention in the past few years. However, most recent work assumed flat hierarchy. This…”
Get full text

A Parallel GPU Implementation of the Timber Wolf Placement Algorithm by Al-Kawam, Ahmad, Harmanani, Haidar M.

“…GPUs have been gaining acceptance in the electronic design automation field as attractive platforms for implementing and accelerating computationally extensive…”
Get full text

A neural networks algorithm for data path synthesis by Harmanani, Haidar M.

“…This paper presents a deterministic parallel algorithm to solve the data path allocation problem in high-level synthesis. The algorithm is driven by a motion…”
Get full text

Efficient shaped quantizer dithering implementation for sigma delta modulators by Anabtawi, Nijad, Ferzli, Rony, Harmanani, Haidar M.

“…A well-known limitation of sigma delta modulators is the generation of limit cycle oscillations for DC and slow varying inputs. These limit cycles give rise to…”
Get full text

An optimal formulation for test scheduling network-on-chip using multiple clock rates by Salamy, Hassan, Harmanani, Haidar M.

“…With the growing trend of increasing number of cores on a single chip, bus-based communication is suffering from bandwidth and scalability issues. As a result,…”
Get full text

A method for efficient mapping and reliable routing for NoC architectures with minimum bandwidth and area by Harmanani, H.M., Farah, R.

“…Network-on-chip (NoC) is an on-chip communication methodology that has been proposed as an alternative to bus-based communication in order to cope with the…”
Get full text

An approach for redesign for testability at the register-transfer level by Harmanani, Haidar M, Harfoush, Salam

“…This paper presents a new approach for redesign for testability at the register-transfer level (RTL). The method identifies hard-to-test past in RTL designs…”
Get full text

Estimating test cost during data path and controller synthesis with low power overhead by Harmanani, H M, Kodeih, M

“…This paper presents a method for concurrent BIST cost estimation during testable data path allocation. The method integrates testability in the design process…”
Get full text

An Ant Colony Optimization approach for test pattern generation by Farah, R., Harmanani, H.M.

“…Test pattern generation is a challenging problem that has an exponential complexity that is aggravated with the continuous increase in circuits size. This…”
Get full text

Integrating wrapper design, TAM assignment, and test scheduling for SOC test optimization by Harmanani, H.M., Farah, R.

“…Test time minimization for core-based designs is tightly integrated with wrapper design and TAM capacity. This paper presents a method to determine minimum SOC…”
Get full text

Resource allocation and reallocation techniques in high-level synthesis with testability constraints by Harmanani, Haidar M

“…The increase in density that the advent of Very Large Scale Integration (VLSI) has allowed, made the move to higher levels of design abstraction imperative…”
Get full text