Search Results - "Haniotakis, T."

A Methodology for Transistor-Efficient Supergate Design by Kagaris, D., Haniotakis, T.

“…The number of transistors required for the implementation of a logic function is a fundamental consideration in digital VLSI design. While the determination of…”
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A Design Technique for Energy Reduction in NORA CMOS Logic by Limniotis, K., Tsiatouhas, Y., Haniotakis, T., Arapoyanni, A.

“…In this work, a design technique to reduce the energy consumption in NO RAce (NORA) circuits is presented. The technique is based on a unidirectional switch…”
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Testable Designs of Multiple Precharged Domino Circuits by Haniotakis, T., Tsiatouhas, Y., Nikolos, D., Efstathiou, C.

“…Domino CMOS circuits are an option for speeding up critical units. An inherent problem of Domino logic is that under specific input conditions the charge…”
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A unified framework for generating all propagation functions for logic errors and events by Michael, M.K., Haniotakis, T., Tragoudas, S.

“…We present a generic framework that supports efficient generation of the traditional Boolean difference function of some output with respect to any line in a…”
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Memory write speed up via multi voltage driver on CeidMem Library by Simopoulos, T., Haniotakis, T., Alexiou, G.Ph

“…A speedup technique for the write function of static memories, achieved via multi voltage manipulation, is presented. The designs created to support this…”
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CeidMem: A compact Static Memory Library by Simopoulos, T., Haniotakis, T., Alexiou, G. Ph

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Efficient totally self-checking checkers for a class of Borden codes by Haniotakis, T., Paschalis, A., Nikolos, D.

“…In this paper a new method to design totally self-checking (TSC) checkers for a class of Borden codes is given and their applicability is discussed. The TSC…”
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Path delay fault testing of ICs with embedded intellectual property blocks by Nikolos, D., Haniotakis, T., Vergos, H.T., Tsiatouhas, Y.

“…In this paper we show that the already known method of using multiplexers for making the inputs and outputs of the embedded blocks accessible by the primary…”
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Security enhancement through multiple path transmission in ad hoc networks by Haniotakis, T., Tragoudas, S., Kalapodas, C.

“…We propose a novel way to further secure the data transmitted along routes of a wireless ad hoc network, after a potentially secure connection has been…”
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Testable designs of one-count generators by HANIOTAKIS, TH, PASCHALIS, A., HALATSIS, C., PHILOKYPROU, G.

“…Testable realizations of One-Count Generators (OCGs) with respect to an extended fault model, including the stuck-at, transistor stuck-open, and transistor…”
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Design and evaluation of a security scheme for sensor networks by Stewart, K., Haniotakis, T., Tragoudas, S.

“…A keyless methodology to ensure secure data transmission in a network of sensors is presented. The main feature is the low power consumption due to the…”
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Fast, parallel two-rail code checker with enhanced testability by Matakias, S., Arapoyanni, A., Efthymiou, A., Tsiatouhas, Y., Haniotakis, T.

“…A current mode, periodic outputs, parallel two-rail code (TRC) checker, suitable for high n-variable (high fan-in) implementations, is presented. The checker…”
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A new dynamic circuit design technique for high performance TSC checker implementations [totally self checking circuits] by Rao, A., Haniotakis, T., Tsiatouhas, Y., Kaky, V.

“…The use of a fault model that handles transistor level faults like transistor stuck-open and transistor stuck-on is highly desirable in modern designs…”
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A hierarchical architecture for concurrent soft error detection based on current sensing by Tsiatouhas, Y., Arapoyanni, A., Nikolos, D., Haniotakis, T.

“…Robust circuit design techniques with respect to soft errors gain importance in the era of very deep submicron technologies. On-line testing will play an…”
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A Current Mode, Parallel, Two-Rail Code Checker by Matakias, Sotirios, Tsiatouhas, Yiorgos, Haniotakis, Themistoklis, Arapoyanni, Angela

“…A current mode, periodic outputs, parallel two-rail code (TRC) checker, suitable for the implementation of high fan-in embedded checkers, is presented. The new…”
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A low power NORA circuit design technique based on charge recycling by Tsiatouhas, Y., Limniotis, K., Arapoyanni, A., Haniotakis, T.

“…In this paper we present a low power oriented design technique for NORA clocked circuits. This technique is based on a new switching scheme for charge…”
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Concurrent detection of soft errors based on current monitoring by Tsiatouhas, Y., Haniotakis, T., Nikolos, D., Efstathiou, C.

“…Transient faults in future ICs turns to be a major consideration as the silicon process scales down. In this paper we propose a new soft error detecting…”
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New test pattern generation units for NPSF oriented memory built-in self test by Chrisarithopoulos, A., Haniotakis, T., Tsiatouhas, Y., Arapoyanni, A.

“…In this paper we present the design of deterministic test pattern generation (TPG) units which can be exploited in a built-in self-test (BIST) scheme for…”
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A Metric for Weight Assignment to Optimize the Performance of MOBILE Threshold Logic Gate by Dara, C. B., Tragoudas, S., Haniotakis, T.

“…The first contribution of the proposed approach is to characterize the temporal behavior of a MOBILE threshold logic gate. Subsequently, we derive a simplified…”
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New memory sense amplifier designs in CMOS technology by Tsiatouhas, Y., Chrisanthopoulos, A., Kamoulakos, G., Haniotakis, T.

“…In this paper two-stage sense amplifier designs are proposed which are suitable for current sensing in SRAM and flash memories read operations. The first-stage…”
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