Search Results - "Hamai, T."

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  1. 1

    A 40-Mpixel/s bit block transfer graphics processor by Sumi, M., Tanaka, S., Kai, N., Miyazawa, Y., Nagamatsu, M., Minagawa, T., Nagashima, I., Hamai, T., Mori, J., Noguchi, T.

    Published in IEEE journal of solid-state circuits (01-06-1989)
    “…A man-machine-interface-oriented graphics processor featuring data transfer speed of over 40 picture/s and character-front bit-mapped speed of over 15000…”
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    Journal Article
  2. 2

    A compaction method for full chip VLSI layouts by Dao, Joseph, Matsumoto, Nobu, Hamai, Tsuneo, Ogawa, Chusei, Mori, Shojiro

    Published in 30th ACM/IEEE Design Automation Conference (01-07-1993)
    “…An algorithm independent layout compaction method for full chip layouts is proposed. The partitioning compaction method cuts up a large layout, compacts each…”
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    Conference Proceeding
  3. 3

    ITU-T recommendations on peer-to-peer (P2P) network security by Hamai, T., Fujii, M., Watanabe, Yu

    “…Peer-to-peer (P2P) networks use diverse connectivity between participants in networks. P2P networks are useful for many purposes. Sharing content files…”
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    Conference Proceeding
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    Theoretical study on the intermodulation interference between wide-band mobile radio systems and narrow-band mobile radio systems by Nakazawa, I., Kobayashi, Y., Shimada, R., Youkai, T., Hamai, T., Murakami, K., Ogawa, H.

    “…At starting of the service operation of 2 GHz band IMT-2000 system in Japan, it is important to make clear the mutual interference problem which may occur…”
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    Conference Proceeding
  11. 11

    Frame timing detection by an MMSE adaptive array for multipath OFDM signals by Song Shi, Hao Yuan, Ohseki, T., Hamai, T.

    “…A timing detection scheme for multipath signals is proposed for wireless OFDM systems. The multipath signal timings are obtained in the process of suppressing…”
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    Conference Proceeding
  12. 12

    Bit map control processor (BMCP) design by Sumi, M., Kai, N., Tanaka, S., Minagawa, T., Nagashima, I., Hamai, T., Mori, J.

    “…A graphic processor, featuring 320-Mb/s bit BLT (bit boundary block transfer) speed, was developed using a novel memory cycle scheme. The key to the system…”
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    Conference Proceeding
  13. 13

    Design of a CMOS token ring LAN controller, TRC, compatible with IEEE802.5 MAC protocol by Yaguchi, Fujimoto, Katsumata, Tanaka, Tamaru, Kanuma, Katagiri, Nishikawa, Shiraishi, Yamamoto, Kimura, Terui, Hamai

    Published in Symposium 1989 on VLSI Circuits (1989)
    “…Token ring has been increasing its importance among LAN (local area network) protocol as the need for deterministic response and low cost wirings continues to…”
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    Conference Proceeding