Search Results - "Hall, Mary W."

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  1. 1

    Maximizing multiprocessor performance with the SUIF compiler by Hall, M. W., Anderson, J. M., Amarasinghe, S. P., Murphy, B. R., Shih-Wei Liao, Bugnion, Edward, Lam, M. S.

    Published in Computer (Long Beach, Calif.) (01-12-1996)
    “…This article describes automatic parallelization techniques in the SUIF (Stanford University Intermediate Format) compiler that result in good multiprocessor…”
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    Journal Article
  2. 2

    Custom Data Layout for Memory Parallelism by So, Byoungro, Hall, Mary W., Ziegler, Heidi E.

    “…In this paper, we describe a generalized approach toderiving a custom data layout in multiple memory banksfor array-based computations, to facilitate…”
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    Conference Proceeding
  3. 3

    Empirical Optimization for a Sparse Linear Solver: A Case Study by Lee, Yoon-Ju, Diniz, Pedro C., Hall, Mary W., Lucas, Robert

    “…This paper describes initial experiences with semi-automated performance tuning of a sparse linear solver in LS-DYNA, a large, widely used engineering…”
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    Journal Article
  4. 4

    Evaluating automatic parallelization in SUIF by Sungdo Moon, Byoungro So, Hall, M.W.

    “…This paper presents the results of an experiment to measure empirically the remaining opportunities for exploiting loop-level parallelism that are missed by…”
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    Journal Article
  5. 5

    Compiler-generated communication for pipelined FPGA applications by Ziegler, Heidi E., Hall, Mary W., Diniz, Pedro C.

    “…In this paper, we describe a set of compiler analyses and an implementation that automatically map a sequential and un-annotated C program into a pipelined…”
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    Conference Proceeding
  6. 6

    Using estimates from behavioral synthesis tools in compiler-directed design space exploration by So, Byoungro, Diniz, Pedro C., Hall, Mary W.

    “…This paper considers the role of performance and area estimates from behavioral synthesis in design space exploration. We have developed a compilation system…”
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    Conference Proceeding
  7. 7

    Adaptive parallelism in compiler-parallelized code by Hall, Mary W., Martonosi, Margaret

    Published in Concurrency (Chichester, England.) (10-12-1998)
    “…As moderate‐scale multiprocessors become widely used, we foresee an increased demand for effective compiler parallelization and efficient management of…”
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    Journal Article
  8. 8

    Characterizing the memory behavior of compiler-parallelized applications by Torrie, E., Martonosi, M., Chau-Wen Tseng, Hall, M.W.

    “…Compiler-parallelized applications are increasing in importance as moderate-scale multiprocessors become common. This paper evaluates how features of advanced…”
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    Journal Article
  9. 9

    Multiprocessors from a software perspective by Amarasinghe, S.P., Anderson, J.M., Wilson, C.S., Shih-Wei Liao, Murphy, B.R., French, R.S., Lam, M.S., Hall, M.W.

    Published in IEEE MICRO (01-06-1996)
    “…Like many architectural techniques that originated with mainframes. the use of multiple processors in a single computer is becoming popular in workstations and…”
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    Journal Article
  10. 10
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    Self-Configuring Applications for Heterogeneous Systems: Program Composition and Optimization Using Cognitive Techniques by Hall, Mary W., Gil, Yolanda, Lucas, Robert F.

    Published in Proceedings of the IEEE (01-05-2008)
    “…This paper describes several challenges facing programmers of future edge computing systems, the diverse many-core devices that will soon exemplify commodity…”
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    Journal Article
  12. 12

    Compiler-Controlled Caching in Superword Register Files for Multimedia Extension Architectures by Shin, Jaewook, Chame, Jacqueline, Hall, Mary W.

    “…In this paper, we describe an algorithm and implementation of locality optimizations for architectures with instruction sets such as Intel's SSE and Motorola's…”
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    Conference Proceeding
  13. 13

    Memory referencing behavior in compiler-parallelized applications by TORRIE, E, MARTONOSI, M, HALL, M. W, TSENG, C.-W

    “…Compiler-parallelized applications are increasing in importance as moderate-scale multiprocessors become common. An evaluation of how features of advanced…”
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    Journal Article
  14. 14

    Evaluating compiler technology for control-flow optimizations for multimedia extension architectures by Shin, Jaewook, Hall, Mary W., Chame, Jacqueline

    Published in Microprocessors and microsystems (01-06-2009)
    “…This paper addresses how to automatically generate code for multimedia extension architectures in the presence of conditionals. We evaluate the costs and…”
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    Journal Article
  15. 15

    Understanding the Behavior of Pthread Applications on Non-Uniform Cache Architectures by Sachdev, G. S., Sudan, K., Hall, M. W., Balasubramonian, R.

    “…Future scalable multi-core chips are expected to implement a shared last-level cache (LLC) with banks distributed on chip, forcing a core to incur non-uniform…”
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    Conference Proceeding
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    Procedure cloning by Cooper, K.D., Hall, M.W., Kennedy, K.

    “…Procedure cloning is an interprocedural optimization where the compiler creates specialized copies of procedure bodies. The authors examine the problem of…”
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    Conference Proceeding Journal Article
  18. 18

    The ParaScope parallel programming environment by Cooper, K.D., Hall, M.W., Hood, R.T., Kennedy, K., McKinley, K.S., Mellor-Crummey, J.M., Torczon, L., Warren, S.K.

    Published in Proceedings of the IEEE (01-02-1993)
    “…The ParaScope parallel programming environment, developed to support scientific programming of shared-memory multiprocessors, is described. It includes a…”
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    Journal Article
  19. 19

    Interprocedural Compilation of Fortran D by Hall, Mary W., Hiranandani, Seema, Kennedy, Ken, Tseng, Chau-Wen

    “…Fortran D is a version of Fortran extended with data decomposition specifications. It is designed to provide a machine-independent programming model for…”
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    Journal Article
  20. 20

    The potential of computation reuse in high-level optimization of a signal recognition system by Demertzi, M., Diniz, P.C., Hall, M.W., Gilbert, A.C., Yi Wang

    “…This paper evaluates the potential of exploiting computation reuse in a signal recognition system that is jointly optimized from mathematical representation,…”
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    Conference Proceeding