Search Results - "Hakim, M.M.A."

Shallow junctions on pillar sidewalls for sub-100-nm vertical MOSFETs by Gili, E., Uchino, T., Hakim, M.M.A., de Groot, C.H., Buiu, O., Hall, S., Ashburn, P.

“…A simple process for the fabrication of shallow drain junctions on pillar sidewalls in sub-100-nm vertical MOSFETs is described. The key feature of this…”
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Asymmetric gate-induced drain leakage and body leakage in vertical MOSFETs with reduced parasitic capacitance by Gili, E., Kunz, V.D., Uchino, T., Hakim, M.M.A., de Groot, C.H., Ashburn, P., Hall, S.

“…Vertical MOSFETs, unlike conventional planar MOSFETs, do not have identical structures at the source and drain, but have very different gate overlaps and…”
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Effects of neglecting carrier tunneling on electrostatic potential in calculating direct tunneling gate current in deep submicron MOSFETs by Hakim, M.M.A., Haque, A.

“…We investigate the validity of the assumption of neglecting carrier tunneling effects on the self-consistent electrostatic potential in calculating the direct…”
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Depletion-isolation effect in vertical MOSFETs during the transition from partial to fully depleted operation by Hakim, M.M.A., de Groot, C.H., Gili, E., Uchino, T., Hall, S., Ashburn, P.

“…A simulation study is made of floating-body effects (FBEs) in vertical MOSFETs due to depletion isolation as the pillar thickness is reduced from 200 to 10nm…”
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Remote plasma enhanced atomic layer deposition of ZnO for thin film electronic applications by Sultan, S.M., Clark, O.D., Masaud, T.B., Fang, Q., Gunn, R., Hakim, M.M.A., Sun, K., Ashburn, P., Chong, H.M.H.

“…[Display omitted] ► O2 plasma used as reactant in remote plasma enhanced ALD. ► High plasma time and low pressure increases the film Carbon content. ► Due to…”
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Improved sub-threshold slope in short-channel vertical MOSFETs using FILOX oxidation by Hakim, M.M.A., Tan, L., Buiu, O., Redman-White, W., Hall, S., Ashburn, P.

“…This paper investigates the origins of sub-threshold slope degradation in vertical MOSFETs (v-MOSFETs) due to dry etching of the polysilicon surround gate…”
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Accurate modeling of gate capacitance in deep submicron MOSFETs with high- K gate-dielectrics by Hakim, M.M.A., Haque, A.

“…Gate capacitance of metal-oxide-semiconductor devices with ultra-thin high- K gate-dielectric materials is calculated taking into account the penetration of…”
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Lateral crystallization of amorphous silicon by germanium seeding by Hakim, M.M.A., Matko, I., Chenevier, B., Ashburn, P.

“…This paper investigates the time and temperature dependence of amorphous silicon lateral crystallization when polycrystalline germanium is used as a seed…”
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Investigation on short channel GGNMOS ESD protection device for low power IC by Hossain, E., Hossain, E., Chowdhury, S.S., Chowdhury, S. S., Matin, M., Matin, M., Ahmed, A. M., Ahmed, A.M., Hakim, M. M. A., Hakim, M.M.A

“…In this paper, the variation of trigger and hold voltages of electrostatic discharge (ESD) snapback of a 20 nm grounded-gate NMOS (GGNMOS) are analyzed by…”
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Improved sub-threshold slope in RF vertical MOSFETS using a frame gate architecture by Hakim, M.M.A., Uchino, T., R-White, W., Ashburn, P., Tan, L., Buiu, O., Hall, S.

“…We report a CMOS-compatible vertical MOSFET, which incorporates a frame gate architecture suitable for application in RF circuits. Fabricated surround gate…”
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Series resistance in vertical MOSFETs with reduced drain/source overlap capacitance by Tan, L., Hall, S., Buiu, M.M.A., Hakim, M.M.A., Uchino, T., Ashburn, P., Redman-White, W.

“…In this work we investigate the series resistances in vertical MOSFETs incorporating the fillet local oxidation (FILOX) structure that serves to reduce the…”
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