Search Results - "Haberl, O."
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HIST: A METHODOLOGY FOR THE AUTOMATIC INSERTION OF A HIERARCHICAL SELF TEST
Published in Proceedings International Test Conference 1992 (1992)Get full text
Conference Proceeding
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A methodology for the insertion of a hierarchical and boundary-scan compatible self test
Published in Digest of Papers. 1992 IEEE VLSI Test Symposium (1992)“…A methodology is presented, which automatically embeds a self test architecture into hierarchically designed circuits. For each module of the design hierarchy…”
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Conference Proceeding -
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The CADEC VLSI design support methodology
Published in CompEuro 1992 Proceedings Computer Systems and Software Engineering (1992)“…The authors address the problem of design flow management with special emphasis on tool selection strategies. To solve this problem the concept and…”
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Conference Proceeding -
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COSIMA: a self-testable simulated annealing processor for universal cost functions
Published in Euro ASIC '92 (1992)“…Presents a chip forming the heart of a special purpose coprocessing unit, which accelerates simulated annealing algorithms to solve combinatorial optimization…”
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Conference Proceeding Journal Article -
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HIST: A hierarchical self test methodology for chips, boards, and systems
Published in Journal of electronic testing (01-02-1995)Get full text
Journal Article -
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TESTCHIP: A Chip for Weighted Random Pattern Generation, Evaluation, and Test Control
Published in ESSCIRC '90: Sixteenth European Solid-State Circuits Conference (01-09-1990)“…A chip is presented that generates weighted random patterns, applies them to a circuit under test and evaluates the test responses. The generated test patterns…”
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Conference Proceeding