Search Results - "HOKAZONO, A"

Forward Body Biasing as a Bulk-Si CMOS Technology Scaling Strategy by Hokazono, A., Balasubramanian, S., Ishimaru, K., Ishiuchi, H., Hu, C., Liu, T.-J.K.

“…Forward body biasing is a promising approach for realizing optimum threshold-voltage ( V TH ) scaling in the era when gate dielectric thickness can no longer…”
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Influence of multi-hit capability on quantitative measurement of NiPtSi thin film with laser-assisted atom probe tomography by Kinno, T., Akutsu, H., Tomita, M., Kawanaka, S., Sonehara, T., Hokazono, A., Renaud, L., Martin, I., Benbalagh, R., Sallé, B., Takeno, S.

“…► Laser-assisted atom probe tomography was applied to NiPtSi films on Si substrates. ► Comparison of depth profiles of single-hit events and those of multi-hit…”
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MOSFET hot-carrier reliability improvement by forward-body bias by Hokazono, A., Balasubramanian, S., Ishimaru, K., Ishiuchi, H., Chenming Hu, Tsu-Jae King Liu

“…Active threshold voltage V/sub TH/ control via well-substrate biasing can be utilized to satisfy International Roadmap for Semiconductors performance and…”
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MOSFET design for forward body biasing scheme by Hokazono, A., Balasubramanian, S., Ishimaru, K., Ishiuchi, H., Tsu-Jae King Liu, Chenming Hu

“…Forward body biasing is a solution for continued scaling of bulk-Si CMOS technology. In this letter, the dependence of 30-nm-gate MOSFET performance on body…”
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High-preformance diamond surface-channel field-effect transistors and their operation mechanism by Tsugawa, K, Kitatani, K, Noda, H, Hokazono, A, Hirose, K, Tajima, M, Kawarada, H

“…Metal–semiconductor (MES) field-effect transistors (FETs) and metal oxide–semiconductor (MOS) FETs are fabricated using p-type conductive layers on…”
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High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide by Inaba, S., Okano, K., Matsuda, S., Fujiwara, M., Hokazono, A., Adachi, K., Ohuchi, K., Suto, H., Fukui, H., Shimizu, T., Mori, S., Oguma, H., Murakoshi, A., Itani, T., Iinuma, T., Kudo, T., Shibata, H., Taniguchi, S., Takayanagi, M., Azuma, A., Oyamatsu, H., Suguro, K., Katsumata, Y., Toyoshima, Y., Ishiuchi, H.

“…The 35 nm gate length CMOS devices with oxynitride gate dielectric and Ni salicide have been fabricated to study the feasibility of higher performance…”
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Enhancement/depletion MESFETs of diamond and their logic circuits by Hokazono, A., Ishikura, T., Nakamura, K., Yamashita, S., Kawarada, H.

“…Using the p-type surface-conductive layer of diamond film, enhancement mode and depletion mode MESFETs have been fabricated by changing the metals of the gate…”
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Steep channel & Halo profiles utilizing boron-diffusion-barrier layers (Si:C) for 32 nm node and beyond by Hokazono, A., Itokawa, H., Kusunoki, N., Mizushima, I., Inaba, S., Kawanaka, S., Toyoshima, Y.

“…Si:C layers under non-doped-Si epitaxial channel (Epi-channel) produces steep channel profile for 25 nm-L G nMOSFET. Si:C layers work as the…”
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Surface p-channel metal-oxide-semiconductor field effect transistors fabricated on hydrogen terminated (001) surfaces of diamond by Hokazono, A, Tsugawa, K, Umezana, H, Kitatani, K, Kawarada, H

“…Metal-oxide-semiconductor field effect transistors (MOSFETs) with a surface p-channel have been fabricated on hydrogen-terminated diamond (001) surfaces…”
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SODEL FET: novel channel and source/drain profile engineering schemes by selective Si epitaxial growth technology by Inaba, S., Miyano, K., Nagano, H., Hokazono, A., Ohuchi, K., Mizushima, I., Oyamatsu, H., Tsunashima, Y., Ishimaru, K., Toyoshima, Y., Ishiuchi, H.

“…In this paper, novel channel and source/drain profile engineering schemes are proposed for sub-50-nm bulk CMOS applications. This device, referred to as the…”
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A hp22 nm node low operating power (LOP) technology with sub-10 nm gate length planar bulk CMOS devices by Yasutake, N., Ohuchi, K., Fujiwara, M., Adachi, K., Hokazono, A., Kojima, K., Aoki, N., Suto, H., Watanabe, T., Morooka, T., Mizuno, H., Magoshi, S., Shimizu, T., Mori, S., Oguma, H., Sasaki, T., Ohmura, M., Miyano, K., Yamada, H., Tomita, H., Matsushita, D., Muraoka, K., Inaba, S., Takayanagi, M., Ishimaru, K., Ishiuchi, H.

“…High performance 10 nm gate length CMOSFETs for hp22 nm node LOP is demonstrated for the first time. Key process, such as elevated source/drain extension…”
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Device modeling of high performance diamond MESFETs using p-type surface semiconductive layers by Noda, H., Hokazono, A., Kawarada, H.

“…The operation of high-performance diamond MESFETs using thin p-type surface semiconductive layers of undoped hydrogen-terminated CVD diamond films has been…”
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Surface morphology and surface p-channel field effect transistor on the heteroepitaxial diamond deposited on inclined β-SiC(001) surfaces by Kawarada, H., Wild, C., Herres, N., Koidl, P., Mizuochi, Y., Hokazono, A., Nagasawa, H.

“…The effect of an inclined substrate on heteroepitaxial diamond has been investigated on 4° off β-SiC(001) tilted around the [1̄10] axis. Homogeneous macro…”
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Electrically isolated metal-semiconductor field effect transistors and logic circuits on homoepitaxial diamonds by KAWARADA, H, ITOH, M, HOKAZONO, A

“…Isolated metal-semiconductor field effect transistors (MESFETs) have been fabricated on homoepitaxial diamonds grown by microwave plasma chemical vapor…”
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150 GHz FMAX with high drain breakdown voltage immunity by multi gate oxide dual work-function (MGO-DWF)-MO SFET by Miyata, T., Tanaka, H., Kagimoto, K., Kamiyashiki, M., Kamimura, M., Hidaka, A., Goto, M., Adachi, K., Hokazono, A., Ohguro, T., Nagaoka, K., Watanabe, Y., Hirooka, S., Ito, Y., Kawanaka, S., Ishimaru, K.

“…We propose Multi Gate Oxide - Dual Work-Function (MGO-DWF)-MOSFET which is suitable for low power AB-class RF power amplifier (RF PA). This was examined for…”
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Steep channel profiles in n/pMOS controlled by boron-doped Si:C layers for continual bulk-CMOS scaling by Hokazono, A., Itokawa, H., Mizushima, I., Kawanaka, S., Inaba, S., Toyoshima, Y.

“…Steep channel impurity-profiles formed by Si:C+Si epitaxial growth have been extensively studied. Especially in pMOS, several concerns are solved by…”
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25-nm Gate Length nMOSFET With Steep Channel Profiles Utilizing Carbon-Doped Silicon Layers (A P-Type Dopant Confinement Layer) by Hokazono, A, Itokawa, H, Kusunoki, N, Mizushima, I, Inaba, S, Kawanaka, S, Toyoshima, Y

“…Steep channel profiles of scaled transistors are a promising approach for advancing transistor generation in bulk complementary metal-oxide-semiconductor…”
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Mechanism of Contact Resistance Reduction in Nickel Silicide Films by Pt Incorporation by Sonehara, T., Hokazono, A., Akutsu, H., Sasaki, T., Uchida, H., Tomita, M., Kawanaka, S., Inaba, S., Toyoshima, Y.

“…Platinum (Pt) incorporation into nickel silicide (NiSi) films improves silicide characteristics such as lower contact resistance RC at silicide/Si interface…”
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Application and device modeling of diamond FET using surface semiconductive layers by Tsugawa, K., Noda, H., Hokazono, A., Kitatani, K., Morita, K., Kawarada, H.

“…Hydrogen‐terminated diamond surfaces exhibit p‐type conduction without doping impurities. The surface conductive layers possess a suitable thickness of ∼ 10 nm…”
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Scaling strategy for low power RF applications with multi gate oxide Dual Work function (DWF) MOSFETs utilizing self-aligned integration scheme by Miyata, T., Kawanaka, S., Hokazono, A., Ohguro, T., Toyoshima, Y.

“…Dual Work Function (DWF)-MOSFET of 100 nm gate length device with self-aligned integration scheme was demonstrated utilizing conventional CMOS platform process…”
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