Search Results - "HELLINGS, G"

Trapping of Hot Carriers in the Forksheet FET Wall: A TCAD Study by Vandemaele, M., Kaczer, B., Tyaginov, S., Franco, J., Bury, E., Chasin, A., Makarov, A., Hellings, G., Groeseneken, G.

“…We simulate the spatial profile of trapped charge in the forksheet FET wall under hot-carrier stress by calculating carrier distribution functions and using a…”
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Increasing Functionality of Wafer’s Backside: Analysis of Si and WS₂ Backside Power-Switch by Mirabelli, G., Chen, R., Ahmed, Z., Chehab, B., Zografos, O., Hiblot, G., Weckx, P., Hellings, G., Ryckaert, J.

“…Recent technological advancements have shown the potential benefits of a backside power-delivery network. Bringing the power much closer to the active logic…”
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Monte Carlo Analysis of -Type SiGe-Channel Nanosheet Performance by Bufler, F. M., Arimura, H., Favia, P., Eneman, G., Matagne, P., Horiguchi, N., Hellings, G.

“…The performance of Si0.75Ge0.25-channel [Formula Omitted]-type nanosheet (NS) devices with a gate length of 14 nm and a sheet width of 12 nm is investigated by…”
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Monte Carlo Comparison of n-Type and p-Type Nanosheets With FinFETs: Effect of the Number of Sheets by Bufler, F. M., Jang, D., Hellings, G., Eneman, G., Matagne, P., Spessot, A., Na, M. H.

“…Analytic doping profiles and contact resistivities are adjusted to reproduce measured transfer characteristics of state-of-the-art n-type and p-type FinFETs by…”
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Self-Heating in iN8-iN2 CMOS Logic Cells: Thermal Impact of Architecture (FinFET, Nanosheet, Forksheet and CFET) and Scaling Boosters by Vermeersch, B., Bury, E., Xiang, Y., Schuddinck, P., Bhuwalka, K. K., Hellings, G., Ryckaert, J.

“…Continuous CMOS scaling enabled by complex transistor topology raises self-heating concerns. Here, we perform a comparative thermal benchmarking of…”
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Upcoming Challenges of ESD Reliability in DTCO with BS-PDN Routing via BPRs by Chen, W.-C., Chen, S.-H., Veloso, A., Serbulova, K., Hellings, G., Groeseneken, G.

“…In this paper, the impact of double-sided connectivity and buried power rails (BPR) on electrostatic discharge (ESD) diodes is reported. Connection from the…”
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3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability by Vandooren, A., Franco, J., Parvais, B., Wu, Z., Witters, L., Walke, A., Li, W., Peng, L., Deshpande, V., Bufler, F. M., Rassoul, N., Hellings, G., Jamieson, G., Inoue, F., Verbinnen, G., Devriendt, K., Teugels, L., Heylen, N., Vecchio, E., Zheng, T., Rosseel, E., Vanherle, W., Hikavyy, A., Chan, B. T., Ritzenthaler, R., Besnard, G., Schwarzenbach, W., Gaudin, G., Radu, I., Nguyen, B.-Y., Waldron, N., De Heyn, V., Mocuta, D., Collaert, N.

“…3-D sequential integration requires top MOSFETs processed at a low thermal budget, which can impair the device reliability. In this paper, top junctionless…”
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Impact of Donor Concentration, Electric Field, and Temperature Effects on the Leakage Current in Germanium p +/n Junctions by Eneman, G., Wiot, M., Brugere, A., Casain, O.S.I., Sonde, S., Brunco, D.P., De Jaeger, B., Satta, A., Hellings, G., De Meyer, K., Claeys, C., Meuris, M., Heyns, M.M., Simoen, E.

“…This paper presents an analysis of junction leakage in heavily doped p+/n germanium junctions, targeted for short-channel transistor fabrication. There exists…”
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PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch by Schuddinck, P., Bufler, F. M., Xiang, Y., Farokhnejad, A., Mirabelli, G., Vandooren, A., Chehab, B., Gupta, A., Neve, C. Roda, Hellings, G., Ryckaert, J.

“…We evaluate Power-Performance-Area & Cost (PPAC) for nanosheet (NS), forksheet (FS), monolithic & sequential Complementary FET (CFET) at 5 & 4 track (T)…”
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Thermal Performance Evaluation of Multi-Core SOCs Using Power-Thermal Co-Simulation by Mishra, S., Vermeersch, B., Sankatali, V., Kukner, H., Sharma, A., Mirabeli, G., Bufler, F. M., Brunion, M., Abdi, D., Oprins, H., Biswas, D., Zografos, O., Catthoor, F., Weckx, P., Hellings, G., Myers, J., Ryckaert, J.

“…Temperature affects performance, power, and en-ergy efficiency in modern system-on-chip (SOC) applications. Transport properties of nanoscale devices are…”
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Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node by Sisto, G., Preston, R., Chen, R., Mirabelli, G., Farokhnejad, A., Zhou, Y., Ciofi, I., Jourdain, A., Veloso, A., Stucchi, M., Zografos, O., Weckx, P., Hellings, G., Ryckaert, J.

“…This paper evaluates the impact of backside power delivery on the physical implementation of a commercial 64-bit high-performance block from ARM™ at the A14…”
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PPA and Scaling Potential of Backside Power Options in N2 and A14 Nanosheet Technology by Yang, S., Schuddinck, P., Garcia-Bardon, M., Xiang, Y., Veloso, A., Chan, B T, Mirabelli, G., Hiblot, G., Hellings, G., Ryckaert, J.

“…This paper evaluates Power-Performance-Area (PPA) tradeoffs and integration challenges of three types of backside power connections: Through Silicon Via in the…”
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Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs) by Mishra, S., Sankatali, V., Vermeersch, B., Brunion, M., Lofrano, M., Abdi, D., Oprins, H., Biswas, D., Zografos, O., Hiblot, G., Van Der Plas, G., Weckx, P., Hellings, G., Myers, J., Catthoor, F., Ryckaert, J.

“…Surge in compute-demand in consumer products, mobile phones, auto mobiles, datacenters for high performance computing (HPC) applications brings in major…”
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Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO by Serbulova, K., Chen, S.-H., Hellings, G., Veloso, A., Jourdain, A., Linten, D., De Boeck, J., Groeseneken, G., Ryckaert, J., Van Der Plas, G., Beyne, E., Litta, E. Dentoni, Horiguchi, N.

“…The primary purpose of continuously scaling the logic technologies is to exploit an optimum performance in various applications. However, technology scaling…”
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Characteristics of cross-sectional atom probe analysis on semiconductor structures by Koelling, S., Innocenti, N., Hellings, G., Gilbert, M., Kambham, A.K., De Meyer, K., Vandervorst, W.

“…The laser-assisted Atom Probe has been proposed as a metrology tool for next generation semiconductor technologies requiring sub-nm spatial resolution. In…”
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Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node by Chen, R., Sisto, G., Stucchi, M., Jourdain, A., Miyaguchi, K., Schuddinck, P., Woeltgens, P., Lin, H., Kakarla, N., Veloso, A., Milojevic, D., Zografos, O., Weckx, P., Hellings, G., Van Der Plas, G., Ryckaert, J., Beyne, E.

“…In this paper, backside power delivery network (BS-PDN) and a high density 2.5D Mimcap (Metal-insulator-metal capacitor) are applied to improve dynamic IR-drop…”
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Reliability and Variability-Aware DTCO Flow: Demonstration of Projections to N3 FinFET and Nanosheet Technologies by Rzepa, G., Karner, M., Baumgartner, O., Strof, G., Schanovsky, F., Mitterbauer, F., Kernstock, C., Karner, H.W., Weckx, P., Hellings, G., Claes, D., Wu, Z., Xiang, Y., Chiarella, T., Parvais, B., Mitard, J., Franco, J., Kaczer, B., Linten, D., Stanojevic, Z.

“…Reliability and variability-aware simulations of logic cells are essential to correctly analyze and predict the performance of upcoming technologies. A…”
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Analysis of the Features of Hot-Carrier Degradation in FinFETs by Makarov, A. A., Tyaginov, S. E., Kaczer, B., Jech, M., Chasin, A., Grill, A., Hellings, G., Vexler, M. I., Linten, D., Grasser, T.

“…For the first time, hot-carrier degradation (HCD) is simulated in non-planar field-effect transistors with a fin-shaped channel (FinFETs). For this purpose, a…”
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Impact of the Device Geometric Parameters on Hot-Carrier Degradation in FinFETs by Tyaginov, S. E., Makarov, A. A., Kaczer, B., Jech, M., Chasin, A., Grill, A., Hellings, G., Vexler, M. I., Linten, D., Grasser, T.

“…The effect of the geometric parameters of Fin field-effect transistors (FinFETs) on hot-carrier degradation (HCD) in these devices is theoretically studied. To…”
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High Performance 70-nm Germanium pMOSFETs With Boron LDD Implants by Hellings, G., Mitard, J., Eneman, G., De Jaeger, B., Brunco, D.P., Shamiryan, D., Vandeweyer, T., Meuris, M., Heyns, M.M., De Meyer, K.

“…Ge pMOSFETs with gate lengths down to 70 nm are fabricated in a Si-like process flow. Reducing the LDD junction depth from 24 to 21 nm effectively reduces…”
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