Tools and Techniques for Implementation of Real-time Video Processing Algorithms

This paper describes flexible tools and techniques that can be used to efficiently design/generate quite a variety of hardware IP blocks for highly parameterized real-time video processing algorithms. The tools and techniques discussed in the paper include host software, FPGA interface IP (PCIe, USB...

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Bibliographic Details
Published in:	Journal of signal processing systems Vol. 91; no. 1; pp. 93 - 113
Main Authors:	Levent, Vecdi Emre, Guzel, Aydin E., Tosun, Mustafa, Buyukmihci, Mert, Aydin, Furkan, Gören, Sezer, Erbas, Cengiz, Akgün, Toygar, Ugurdag, H. Fatih
Format:	Journal Article
Language:	English
Published:	New York Springer US 2019 Springer Nature B.V
Subjects:	Algorithms Circuits and Systems Computer Imaging Data buses Electrical Engineering Engineering Field programmable gate arrays Hardware High level synthesis Image processing Image Processing and Computer Vision Optical flow (image analysis) Pattern Recognition Pattern Recognition and Graphics Real time Signal,Image and Speech Processing Video Vision Real-time video processing High-level synthesis Hardware IP generation FPGA Nested pipelining Optical flow
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Summary:	This paper describes flexible tools and techniques that can be used to efficiently design/generate quite a variety of hardware IP blocks for highly parameterized real-time video processing algorithms. The tools and techniques discussed in the paper include host software, FPGA interface IP (PCIe, USB 3.0, DRAM), high-level synthesis, RTL generation tools, synthesis automation as well as architectural concepts (e.g., nested pipelining), an architectural estimation tool, and verification methodology. The paper also discusses a specific use case to deploy the mentioned tools and techniques for hardware design of an optical flow algorithm. The paper shows that in a fairly short amount of time, we were able to implement 11 versions of the optical flow algorithm running on 3 different FPGAs (from 2 different vendors), while we generated and synthesized several thousand designs for architectural trade-off.
ISSN:	1939-8018 1939-8115
DOI:	10.1007/s11265-018-1402-7