Search Results - "Gunrae Kim"

Novel Error Detection Scheme With the Harmonious Use of Parity Codes, Well-Taps, and Interleaving Distance by Jeon, Sang Hoon, Lee, Soonyoung, Baeg, Sanghyeon, Kim, Ilgon, Kim, Gunrae

“…This paper explores the effectiveness of error detection schemes in increasingly multiple-cell upset-dominant technologies, specifically SRAM. A review of…”
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Investigation of logic soft error and scaling effect in 10 nm FinFET technology by Uemura, Taiki, Soonyoung Lee, GunRae Kim, Sangwoo Pae

“…This paper presents characterization of soft error in logic circuits manufactured with 10 nm FinFET technology. The 10 nm FinFET technology provides…”
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Technology scaling on High-K & Metal-Gate FinFET BTI reliability by Kyong Taek Lee, Wonchang Kang, Eun-Ae Chung, Gunrae Kim, Hyewon Shim, Hyunwoo Lee, Hyejin Kim, Minhyeok Choe, Nae-In Lee, Patel, Anuj, Junekyun Park, Jongwoo Park

“…High-K (HK) & Metal-Gate (MG) transistor technology have become a mainstream for the logic & SOC processes. On HK/MG process, bias-temp instability (BTI) poses…”
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Soft error rate analysis for incident angle and N-well structure dependencies using small-sized alpha source in 10nm FinFET technology by Soonyoung Lee, Uemura, Taiki, Monga, Udit, Jae Hee Choi, GunRae Kim, Sangwoo Pae

“…Alpha particle-induced soft error rate (alpha-SER) of SRAM built in 10 nm FinFET on bulk technology was characterized. The 10 nm FinFET SRAM devices provide…”
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New insights into 10nm FinFET BTI and its variation considering the local layout effects by Changze Liu, Minjung Jin, Uemura, Taiki, Jinju Kim, Jungin Kim, Ukjin Jung, Hyun Chul Sagong, Gunrae Kim, Junekyun Park, Sangchul Shin, Sangwoo Pae

“…In this paper, BTI variation of 10nm FinFET is experimentally studied taking into account of the local layout effects. Although Fin shape is further optimized…”
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Development of thermal neutron SER-resilient high-k/metal gate technology by Jongwoo Park, Gunrae Kim, Ming Zhang, Kyungsik Park, Miji Lee, Ilgon Kim, Jongsun Bae, Sangwoo Pae, Jinwoo Choi, Dongsuk Shin, Nae-In Lee, Kee Sup Kim

“…We report the experimental procedure and data that establishes the correlation between natural boron (B 10 ) concentration and thermal neutron soft error rate…”
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At speed HTOL test for reliability qualification of high speed mobile applications by Jongwoo Park, Da Ahn, Donghee Lee, Jang, E.-S, Wooyeon Kim, Sangchul Shin, Gunrae Kim, Nae-In Lee, Sangwoo Pae

“…In this paper, intuition is given on the Vmin shift behaviors under high speed frequency high temperature operating life (HTOL) stress conditions on Dual- and…”
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Mature processability and manufacturability by characterizing VT and Vmin behaviors induced by NBTI and AHTOL test by Jongwoo Park, Sungmok Ha, Sunme Lim, Jae-Yoon Yoo, Junkyun Park, Kidan Bae, Gunrae Kim, Min Kim, Yongshik Kim

“…A systematical reliability assessment for technology process that is essential for technology feasibility and qualification is presented by addressing physical…”
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Characterization of plate-like Ni-Sn intermetallic compounds in Sn-Ag solder bump by Hanbyul Kang, Miji Lee, Sangkwon Park, Sangsu Ha, Gunrae Kim, Sangchul Shin, Sangwoo Pae

“…We characterized plate-like Ni-Sn IMCs in the Sn-2.3wt.%Ag solder bump using high-resolution 3D X-ray microscopy and transmission electron microscopy. Two…”
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Reliability characterization of 10nm FinFET technology with multi-VT gate stack for low power and high performance by Minjung Jin, Changze Liu, Jinju Kim, Jungin Kim, Hyewon Shim, Kangjung Kim, Gunrae Kim, Soonyoung Lee, Uemura, Taiki, Man Chang, Taehyun An, Junekyun Park, Sangwoo Pae

“…We report the reliability characterization of 10nm FinFET process technology. Unique reliability behavior by using multi-V T 's through work function…”
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Investigation of BTI characteristics and its behavior on 10 nm SRAM with high-k/metal gate FinFET technology having multi-VT gate stack by Jin, Minjung, Kim, Kangjung, Kim, Yoohwan, Shim, Hyewon, Kim, Jinju, Kim, Gunrae, Pae, Sangwoo

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Investigation of BTI characteristics and its behavior on 10nm SRAM with high-k/metal gate FinFET technology having multi-VT gate stack by Jin, Minjung, Kim, Kangjung, Kim, Yoohwan, Shim, Hyewon, Kim, Jinju, Kim, Gunrae, Pae, Sangwoo

“…Bias-Temperature Instability (BTI) is one of the key device reliability concerns for both digital and analog circuit operations. Features of work-function…”
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Soft-Error Susceptibility in Flip-Flop in EUV 7 nm Bulk-FinFET Technology by Uemura, Taiki, Chung, Byungjin, Jo, Jeongmin, Kim, Mijoung, Lee, Dalhee, Kim, Gunrae, Lee, Seungbae, Song, Taesjoong, Rhee, Hwasung, Lee, Brandon, Choi, Jaehee

“…This paper presents single-event upset (SEU) rates in flip-flops (FFs) in EUV 7 nm bulk-FinFET technology. EUV technology achieves high transistor-density,…”
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