Search Results - "Guarini, K. W."

Integration of self-assembled diblock copolymers for semiconductor capacitor fabrication by Black, C. T., Guarini, K. W., Milkove, K. R., Baker, S. M., Russell, T. P., Tuominen, M. T.

“…We combine a self-organizing diblock copolymer system with semiconductor processing to produce silicon capacitors with increased charge storage capacity over…”
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Growth of Silicon Oxide in Thin Film Block Copolymer Scaffolds by Kim, D. H., Jia, X., Lin, Z., Guarini, K. W., Russell, T. P.

“…Thin films of asymmetric diblock copolymers have been used as scaffolds to define an ordered array of nanometer‐scale reaction vessels in which high density…”
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Effect of tensile uniaxial stress on the electron transport properties of deeply scaled FD-SOI n-type MOSFETs by Nayfeh, H.M., Singh, D.V., Hergenrother, J.M., Sleight, J.W., Ren, Z., Dokumaci, O., Black, L., Chidambarrao, D., Venigalla, R., Pan, J., Natzle, W., Tessier, B.L., Ott, J.A., Khare, M., Guarini, K.W., Ieong, M., Haensch, W.

“…The effect of longitudinal uniaxial mechanical stress on electron mobility in high-performance fully depleted ultrathin silicon-on-insulator nFETs with a…”
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High-quality crystalline layer transfer from a silicon-on-insulator substrate onto a sapphire substrate using wafer bonding by SINGH, D. V, SHI, L, GUARINI, K. W, MOONEY, P. M, KOESTER, S. J, GRILL, A

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Optimization of Diblock Copolymer Thin Film Self Assembly by Guarini, K.W., Black, C.T., Yeung, S.H.I.

“…How can optimum long‐range order be achieved by self‐assembly of polystyrene/polymethylmethacrylate (PS/PMMA) block copolymers? Here the film thickness,…”
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Process integration of self-assembled polymer templates into silicon nanofabrication by Guarini, K. W., Black, C. T., Zhang, Y., Kim, H., Sikorski, E. M., Babich, I. V.

“…Self-assembled diblock copolymer thin films are used as sacrificial layers for the transfer of dense nanoscale patterns into more robust materials. We detail…”
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Structural evolution of cylindrical-phase diblock copolymer thin films by Black, C. T., Guarini, K. W.

“…We have measured the time evolution of the self‐assembly process in perpendicular‐oriented cylindrical‐phase diblock copolymer thin films using statistical…”
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Nanoscale patterning using self-assembled polymers for semiconductor applications by Guarini, K. W., Black, C. T., Milkove, K. R., Sandstrom, R. L.

“…Thin films of self-organizing diblock copolymers may be suitable for semiconductor applications since they enable patterning of ordered domains with dimensions…”
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High-capacity, self-assembled metal-oxide-semiconductor decoupling capacitors by Black, C.T., Guarini, K.W., Ying Zhang, Hyungjun Kim, Benedict, J., Sikorski, E., Babich, I.V., Milkove, K.R.

“…We combine nanometer-scale polymer self assembly with advanced semiconductor microfabrication to produce metal-oxide-semiconductor (MOS) capacitors with…”
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Microfabricated silicon solid immersion lens by Fletcher, D.A., Crozier, K.B., Guarini, K.W., Minne, S.C., Kino, G.S., Quate, C.F., Goodson, K.E.

“…We present the microfabrication of a solid immersion lens from silicon for scanning near-field optical microscopy. The solid immersion lens (SIL) achieves…”
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High performance FDSOI CMOS technology with metal gate and high-k by Doris, B., Kim, Y.H., Linder, B.P., Steen, M., Narayanan, V., Boyd, D., Rubino, J., Chang, L., Sleight, J., Topol, A., Sikorski, E., Shi, L., Wong, L., Babich, K., Zhang, Y., Kirsch, P., Newbury, J., Walker, J.F., Carruthers, R., D'Emic, C., Kozlowski, P., Jammy, R., Guarini, K.W., Leong, M.

“…A high performance FDSOI CMOS technology featuring metal gate electrodes and high-k gate dielectrics is presented. Work-function tuning is accomplished by…”
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Mobility and CMOS devices/circuits on sub-10nm [110] ultra thin body SOI by Huiling Shang, Rubino, J., Doris, B., Topol, A., Sleight, J., Cai, J., Chang, L., Ott, A., Kedzierski, J., Chan, K., Shi, L., Babich, K., Newbury, J., Sikorski, E., To, B.N., Zhang, Y., Guarini, K.W., Meikei Ieong

“…For the first time, we show the experimental inversion mobility data on ultra thin [110] SOI substrates for thickness as thin as 6nm. Both electron and hole…”
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Effect of contact liner stress in high-performance FDSOI devices with ultra-thin silicon channels and 30 nm gate lengths by Singh, D.V., Hergenrother, J.M., Sleight, J.W., Ren, Z., Nayfeh, H., Dokumaci, O., Black, L., Chidambarrao, D., Venigalla, R., Pan, J., Tessier, B.L., Nomura, A., Ott, J.A., Khare, M., Guarini, K.W., Ieong, M., Haensch, W.

“…We have investigated for the first time the effect of stressed contact liners on the performance of fully depleted ultra-thin channel CMOS devices with a…”
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Stable SRAM cell design for the 32 nm node and beyond by Chang, L., Fried, D.M., Hergenrother, J., Sleight, J.W., Dennard, R.H., Montoye, R.K., Sekaric, L., McNab, S.J., Topol, A.W., Adams, C.D., Guarini, K.W., Haensch, W.

“…SRAM cell stability will be a primary concern for future technologies due to variability and decreasing power supply voltages. 6T-SRAM can be optimized for…”
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Aggressively scaled (0.143 /spl mu/m/sup 2/) 6T-SRAM cell for the 32 nm node and beyond by Fried, D.M., Hergenrother, J.M., Topol, A.W., Chang, L., Sekaric, L., Sleight, J.W., McNab, S.J., Newbury, J., Steen, S.E., Gibson, G., Zhang, Y., Fuller, N.C.M., Bucchignano, J., Lavoie, C., Cabral Jr, C., Canaperi, D., Dokumaci, O., Frank, D.J., Duch, E.A., Babich, I., Wong, K., Ott, J.A., Adams, C.D., Dalton, T.J., Nunes, R., Medeiros, D.R., Viswanathan, R., Ketchen, M., Ieong, M., Haensch, W., Guarini, K.W.

“…A 0.143 /spl mu/m/sup 2/ 6T-SRAM cell has been fabricated using a planar SOI technology with mixed electron-beam and optical lithography. This is the smallest…”
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Scattering Study on the Selective Solvent Swelling Induced Surface Reconstruction by Xu, Ting, Goldbach, James T, Misner, Matthew J, Kim, Seunghyun, Gibaud, Alain, Gang, Oleg, Ocko, Ben, Guarini, Kathryn W, Black, Charles T, Hawker, Craig J, Russell, Thomas P

“…A selective solvent induced surface reconstruction of thin films of an asymmetric diblock copolymer of poly(styrene-b-methyl methacrylate) was investigated by…”
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Two gates are better than one [double-gate MOSFET process] by Solomon, P.M., Hovel, H.J., Bucchignano, J.J., Cabral, C., Lavoie, C., Ku, V., Boyd, D.C., Petrarca, K., Yoon, J.H., Babich, I.V., Treichler, J., Guarini, K.W., Kozlowski, P.M., Newbury, J.S., D'Emic, C.P., Sicina, R.M., Benedict, J., Wong, H.-S.P., Zhang, Y., Chan, K., Jones, E.C., Cohen, G.M., Krasnoperova, A., Ronay, M., Dokumaci, O.

“…A planar self-aligned double-gate MOSFET process has been implemented where a unique sidewall source/drain structure (S/D) permits self-aligned patterning of…”
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Interface studies of tungsten gate metal–oxide–silicon capacitors by Shang, Huiling, White, Marvin H., Guarini, Kathryn W., Solomon, Paul, Cartier, Eduard, McFeely, Fenton R., Yurkas, John J., Lee, Wen-Chin

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Two gates are better than one - double-gate MOSFET process by Solomon, P M, Guarini, K W, Zhang, Y, Chan, K, Jones, E C, Cohen, G M, Krasnoperova, A, Ronay, M, Dokumaci, O, Hovel, H J, Bucchignano, J J, Cabral, C, Lavoie, C, Ku, V, Boyd, D C, Petrarca, K, Yoon, J H, Babich, I V, Treichler, J

“…A planar self-aligned double-gate MOSFET process has been implemented where a unique sidewall source/drain structure (S/D) permits self-aligned patterning of…”
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Triple-self-aligned, planar double-gate MOSFETs: devices and circuits by Guarini, K.W., Solomon, P.M., Zhang, Y., Chan, K.K., Jones, E.C., Cohen, G.M., Krasnoperova, A., Ronay, M., Dokumaci, O., Bucchignano, J.J., Cabral, C., Lavoie, C., Ku, V., Boyd, D.C., Petrarca, K.S., Babich, I.V., Treichler, J., Kozlowski, P.M., Newbury, J.S., D'Emic, C.P., Sicina, R.M., Wong, H.-S.

“…We introduce a planar, triple-self-aligned double-gate FET structure ("PAGODA"). Device fabrication incorporates wafer bonding, front-end CMP, mixed…”
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