Search Results - "Guan Huei See"

A Compact Model for Undoped Silicon-Nanowire MOSFETs With Schottky-Barrier Source/Drain by Zhu, Guojun, Zhou, Xing, Lee, Teck Seng, Ang, Lay Kee, See, Guan Huei, Lin, Shihuan, Chin, Yoke-King, Pey, Kin Leong

“…A comprehensive physics-based compact model for three-terminal undoped Schottky-barrier (SB) gate-all-around silicon-nanowire MOSFETs is formulated based on a…”
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Rigorous Surface-Potential Solution for Undoped Symmetric Double-Gate MOSFETs Considering Both Electrons and Holes at Quasi NonEquilibrium by Xing Zhou, Zhaomin Zhu, Rustagi, S.C., Guan Huei See, Guojun Zhu, Shihuan Lin, Chengqing Wei, Guan Hui Lim

“…This paper presents a rigorously-derived analytical solution of the Poisson equation with both electrons and holes in pure silicon, which is applied to the…”
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"Ground-Referenced" Model for Three-Terminal Symmetric Double-Gate MOSFETs With Source/Drain Symmetry by Guojun Zhu, Guojun Zhu, Guan Huei See, Guan Huei See, Shihuan Lin, Shihuan Lin, Xing Zhou, Xing Zhou

“…This brief presents for the first time a ldquoground-referencedrdquo model to satisfy the Gummel symmetry test in three-terminal MOSFETs without body contact…”
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A Compact Model Satisfying Gummel Symmetry in Higher Order Derivatives and Applicable to Asymmetric MOSFETs by Guan Huei See, Xing Zhou, Chandrasekaran, K., Siau Ben Chiah, Zhaomin Zhu, Chengqing Wei, Shihuan Lin, Guojun Zhu, Guan Hui Lim

“…This paper presents a new concept for the MOSFET saturation voltages at the drain and source sides referenced to bulk, and applies them to the popularly used…”
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A New Impact-Ionization Current Model Applicable to Both Bulk and SOI MOSFETs by Considering Self-Lattice-Heating by Chengqing Wei, Chengqing Wei, Guan Huei See, Guan Huei See, Xing Zhou, Xing Zhou, Lap Chan, Lap Chan

“…In existing impact-ionization current (J sub ) models for short-channel MOSFETs, various models for the characteristic ionization length (I) or the…”
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Under-Bump Metallization Contact Resistance ( R ) Characterization at 10- \mu \text Polymer Passivation Opening by Lianto, Prayudi, King-Jien Chui, Bhushan, Bharat, Chua, H. M. Calvin, Leijun Tang, Chandra Rao, B. S. S., Xin Wang, Ai Long Wu, Yu Gu, Guan Huei See, Sundarrajan, Arvind

“…Under-bump metallization R c is a critical metric for high-density interconnect in electronic devices. We developed a test vehicle to characterize the impact…”
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Physics-based single-piece charge model for strained-Si MOSFETs by Chandrasekaran, K., Xing Zhou, Chiah, S.B., Shangguan, W., Guan Huei See

“…A physics-based single-piece charge model for strained-silicon (s-Si) MOSFETs from accumulation to strong-inversion regions is presented. The model is…”
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Surface-Potential Solution for Generic Undoped MOSFETs With Two Gates by Shangguan, W.Z., Xing Zhou, Chandrasekaran, K., Zhaomin Zhu, Rustagi, S.C., Chiah, S.B., Guan Huei See

“…We present a rigorously derived analytical Poisson solution for undoped semiconductors and apply the general solution to generic MOSFETs with two gates,…”
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Implicit Analytical Surface/Interface Potential Solutions for Modeling Strained-Si MOSFETs by Chandrasekaran, K., Xing Zhou, Siau Ben Chiah, Guan Huei See, Rustagi, S.C.

“…A new technique for calculating surface and interface potentials in heterostructure MOSFETs such as strained-Si/SiGe using an internal iteration approach is…”
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Effect of substrate doping on the capacitance-Voltage characteristics of strained-silicon pMOSFETs by Chandrasekaran, K., Xing Zhou, Chiah, S.B., Shangguan, W., Guan Huei See, Bera, L.K., Balasubramanian, N., Rustagi, S.C.

“…The effect of substrate doping on the capacitance-voltage characteristics of a surface-channel strained-silicon p-channel MOSFET has been studied to explain a…”
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Subcircuit Compact Model for Dopant-Segregated Schottky Gate-All-Around Si-Nanowire MOSFETs by Zhu, Guojun, Zhou, Xing, Chin, Yoke-King, Pey, Kin Leong, Zhang, Junbin, See, Guan Huei, Lin, Shihuan, Yan, Yafei, Chen, Zuhui

“…In this paper, we demonstrate analytical device models and a unique subcircuit approach to physically and accurately model the dopant-segregated Schottky (DSS)…”
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Explicit Compact Surface-Potential and Drain-Current Models for Generic Asymmetric Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistors by Zhu, Zhaomin, Zhou, Xing, Chandrasekaran, Karthik, Rustagi, Subhash C., See, Guan Huei

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Fine-Pitch RDL Integration for Fan-Out Wafer-Level Packaging by Lianto, Prayudi, Tan, Chin Wei, Jie Peng, Qi, Jumat, Abdul Hakim, Dai, Xundong, Peter Fung, Khai Mum, Huei See, Guan, Chong, Ser Choong, Wee David Ho, Soon, Serine Soh, Siew Boon, Huang Sharon Lim, Seow, Calvin Chua, Hung Ming, Abdillah Haron, Ahmad, Kenneth Lee, Huan Ching, Zhang, Mingsheng, Ko, Zhi Hao, Ko San, Ye, Leong, Henry

“…Fan-Out wafer-level packaging (FOWLP) semi-additive process (SAP) flow for three layers of redistribution layer (RDL) has been developed. Patched dicing lane…”
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Evaluation on multiple layer PBO-based Cu RDL process for Fan-Out Wafer Level Packaging (FOWLP) by Soh Siew Boon, Chui, K. J., David Ho, S. W., Sek, S. A., Mingbin Yu, Lianto, Prayudi, Yu Gu, Guan Huei See, Bernt, Marvin L.

“…Fan-Out Wafer Level Packaging (FOWLP) was proposed and introduced due its advantages in cost reduction [1] and enhanced packaging capabilities. However, there…”
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Extraction of physical parameters of strained silicon MOSFETs from C-V measurement by Chandrasekaran, K., Xing Zhou, Siau Ben Chiah, Wangzuo Shangguan, Guan Huei See, Bera, L.K., Balasubramanian, N., Rustagi, S.C.

“…This paper presents a methodology for extraction of the physical parameters of strained-silicon MOSFET from one capacitance-voltage (C-V) measurement based on…”
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aGround-Referenceda Model for Three-Terminal Symmetric Double-Gate MOSFETs With Source/Drain Symmetry by Zhu, Guojun, See, Guan Huei, Lin, Shihuan, Zhou, Xing

“…This brief presents for the first time a "ground-referenced" model to satisfy the Gummel symmetry test in three-terminal MOSFETs without body contact. Unlike…”
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Unified regional modeling approach to emerging multiple-gate/nanowire MOSFETs by Xing Zhou, Guan Huei See, Guojun Zhu, Shihuan Lin, Chengqing Wei, Junbin Zhang

“…This paper reviews the basic governing equations for a double-gate/gate-all-around (DG/GAA) MOSFET in a generic and unified description. Starting from generic…”
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Unification of MOS compact models with the unified regional modeling approach by Zhou, Xing, Zhu, Guojun, See, Guan Huei, Chandrasekaran, Karthik, Chiah, Siau Ben, Lim, Khee Yong

“…This paper reviews the development of the MOSFET model (Xsim), for unification of various types of MOS devices, such as bulk, partially/fully-depleted SOI,…”
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Unified compact modeling for Bulk/SOI/FinFET/SiNW MOSFETs by Xing Zhou, Guojun Zhu, Guan Huei See, Junbin Zhang, Shihuan Lin, Chengqing Wei, Zuhui Chen, Srikanth, M., Yafei Yan, Selvakumar, R., Chandra, W.

“…This paper describes seamless transitions among various MOS devices, ranging from bulk and partially/fully-depleted SOI to double-gate FinFETs and…”
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Unification of MOS compact models with the unified regional modeling approach : Computational Electronics in Asia and Selected Papers from IWCE 2009 in Beijing by XING ZHOU, GUOJUN ZHU, GUAN HUEI SEE, CHANDRASEKARAN, Karthik, SIAU BEN CHIAH, KHEE YONG LIM

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