Search Results - "Greskamp, Brian"
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VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects
Published in IEEE transactions on semiconductor manufacturing (01-02-2008)“…Within-die parameter variation poses a major challenge to high-performance microprocessor design, negatively impacting a processor's frequency and leakage…”
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Unifying on-chip and inter-node switching within the Anton 2 network
Published in 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA) (01-06-2014)“…The design of network architectures has become increasingly complex as the chips connected by inter-node networks have emerged as distributed systems in their…”
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The Specialized High-Performance Network on Anton 3
Published in 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA) (01-04-2022)“…Molecular dynamics (MD) simulation, a computationally intensive method that provides invaluable insights into the behavior of biomolecules, typically requires…”
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Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core Overclocking
Published in 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007) (01-09-2007)“…Under current worst-case design practices, manufacturers specify conservative values for processor frequencies in order to guarantee correctness. To recover…”
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EVAL: Utilizing processors with variation-induced timing errors
Published in 2008 41st IEEE/ACM International Symposium on Microarchitecture (08-11-2008)“…Parameter variation in integrated circuits causes sections of a chip to be slower than others. If, to prevent any resulting timing errors, we design processors…”
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The BubbleWrap many-core: popping cores for sequential acceleration
Published in 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) (12-12-2009)“…Many-core scaling now faces a power wall. The gap between the number of cores that fit on a die and the number that can operate simultaneously under the power…”
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Conference Proceeding -
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Blueshift: Designing processors for timing speculation from the ground up
Published in 2009 IEEE 15th International Symposium on High Performance Computer Architecture (01-02-2009)“…Several recent processor designs have proposed to enhance performance by increasing the clock frequency to the point where timing faults occur, and by adding…”
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Threshold Voltage Variation Effects on Aging-Related Hard Failure Rates
Published in 2007 IEEE International Symposium on Circuits and Systems (ISCAS) (01-05-2007)“…This paper quantifies the impact of threshold voltage variation on aging-related hard failure rates in a high-performance 65nm processor. Simulations show that…”
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Conference Proceeding -
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CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging
Published in International Conference on Dependable Systems and Networks (DSN'06) (2006)“…One of the main reasons for the difficulty of hardware verification is that hardware platforms are typically nondeterministic at clock-cycle granularity…”
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LeadOut: Composing low-overhead frequency-enhancing techniques for single-thread performance in configurable multicores
Published in HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture (01-01-2010)“…Despite the ubiquity of multicores, it is as important as ever to deliver high single-thread performance. An appealing way to accomplish this is by shutting…”
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The Specialized High-Performance Network on Anton 3
Published 20-01-2022“…Molecular dynamics (MD) simulation, a computationally intensive method that provides invaluable insights into the behavior of biomolecules, typically requires…”
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Journal Article -
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Improving per-thread performance on CMPs through timing speculation
Published 01-01-2009“…The future of performance scaling lies in massively parallel workloads, but less-parallel applications remain important. Unfortunately, future process…”
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Dissertation -
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Online architectures: A theoretical formulation and experimental prototype
Published in Microprocessors and microsystems (04-09-2006)“…This article describes a class of reconfigurable computing system called online architectures. These architectures use an online algorithm to make run-time…”
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Journal Article -
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Filtering, Reductions and Synchronization in the Anton 2 Network
Published in 2015 IEEE International Parallel and Distributed Processing Symposium (01-05-2015)“…Parallel implementations of molecular dynamics (MD) simulation require significant inter-node communication, but off-chip communication bandwidth is not…”
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Conference Proceeding -
15
The ΛNTON 3 ASIC: a Fire-Breathing Monster for Molecular Dynamics Simulations
Published in 2021 IEEE Hot Chips 33 Symposium (HCS) (22-08-2021)“…* Understand biomolecular systems through their motions *Numerical integration of Newton's laws of motion - Model atoms as point masses - Compute forces on…”
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Improving per-thread performance on CMPs through timing speculation
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Dissertation -
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The ANTON 2 chip a second-generation ASIC for molecular dynamics
Published in 2014 IEEE Hot Chips 26 Symposium (HCS) (01-08-2014)“…This article consists of a collection of slides from the author's conference presentation on the special features, supercomputing capabilities; system design…”
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A Model for Timing Errors in Processors with Parameter Variation
Published in 8th International Symposium on Quality Electronic Design (ISQED'07) (01-03-2007)“…Parameter variation in integrated circuits causes sections of a chip to be slower than others. To prevent any resulting timing errors, designers have…”
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Estimating design time for system circuits
Published in 2007 IFIP International Conference on Very Large Scale Integration (01-10-2007)“…System design complexity is growing rapidly. As a result, current development costs are constantly increasing. It is becoming increasingly difficult to…”
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20
A virtual machine for merit-based runtime reconfiguration
Published in 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) (2005)“…This work advocates a merit-based reconfiguration policy. In the merit-based approach, each kernel that has a hardware implementation also has a software…”
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