Search Results - "Gravot, V."

Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits by Badaroglu, M., van Heijningen, M., Gravot, V., Compiet, J., Donnay, S., Gielen, G.G.E., De Man, H.J.

“…This paper describes substrate noise reduction techniques for synchronous CMOS circuits. Low-noise digital design techniques have been implemented and measured…”
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Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate by Badaroglu, M., Balasubramanian, L., Tiri, K., Gravot, V., Wambacq, P., Van der Plas, G., Donnay, S., Gielen, G., De Man, H.

“…Ground bounce is a major contributor to substrate noise generation due to the resonance caused by the inductance and the VDD-VSS admittance that consists of…”
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A harmonic quadrature LO generator using a 90/spl deg/ delay-locked loop [zero-IF transceiver applications] by Craninckx, J., Gravot, V., Donnay, S.

“…To overcome problems with DC-offsets and LO pulling in zero-IF transceivers, a technique is presented to generate quadrature LO signals from an oscillator…”
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High-level simulation of substrate noise generation from large digital circuits with multiple supplies by Badaroglu, M., van Heijningen, M., Gravot, V., Donnay, S., De Man, H., Gielen, G., Engels, M., Bolsens, I.

“…Substrate noise generated by large digital circuits degrades the performance of analog circuits sharing the same substrate. Existing approaches usually extract…”
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Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits by Badaroglu, M., van Heijningen, M., Gravot, V., Compiet, J., Donnay, S., Engels, M., Gielen, G., De Man, H.

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Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits by Badaroglu, M., van Heijningen, M., Gravot, V., Compiet, J., Donnay, S., Engels, M., Gielen, G., De Man, H.

“…An efficient substrate-noise-reduction technique for synchronous CMOS circuits shows >2/spl times/ noise reduction with penalties of 3% area and 4% power…”
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High-level simulation of substrate noise generation from large digital circuits with multiple supplies by Badaroglu, M., van Heijningen, M., Gravot, V., Donnay, S., De Man, H., Gielen, G., Engels, M., Bolsens, I.

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High-level simulation of substrate noise generation from large digital circuits with multiple supplies by Badaroglu, M, van Heijningen, M, Gravot, V, Donnay, S, De Man, H, Gielen, G, Engels, M, Bolsens, I

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