Search Results - "Goutis, Costas"

A methodology for speeding up matrix vector multiplication for single/multi-core architectures by Kelefouras, Vasilios, Kritikakou, Angeliki, Papadima, Elissavet, Goutis, Costas

“…In this paper, a new methodology for computing the Dense Matrix Vector Multiplication, for both embedded (processors without SIMD unit) and general purpose…”
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Design and implementation of totally-self checking SHA-1 and SHA-256 hash functions’ architectures by Michail, Harris E., Athanasiou, George S., Theodoridis, George, Gregoriades, Andreas, Goutis, Costas E.

“…•Totally Self-Checking (TSC) design for widely used hash function: SHA-1•Totally Self-Checking (TSC) design for widely used hash function: SHA-256•Appropriate…”
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A Methodology for Speeding Up Fast Fourier Transform Focusing on Memory Architecture Utilization by Kelefouras, V. I., Athanasiou, G. S., Alachiotis, N., Michail, H. E., Kritikakou, A. S., Goutis, C. E.

“…Several SOA (state of the art) self-tuning software libraries exist, such as the Fastest Fourier Transform in the West (FFTW) for fast Fourier transform (FFT)…”
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A Methodology for Speeding up MVM for Regular, Toeplitz and Bisymmetric Toeplitz Matrices by Kelefouras, Vasilios I., Kritikakou, Angeliki S., Siourounis, Konstantinos, Goutis, Costas E.

“…The Matrix Vector Multiplication algorithm is an important kernel in most varied domains and application areas and the performance of its implementations…”
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Resource aware mapping on coarse grained reconfigurable arrays by Dimitroulakos, Grigorios, Georgiopoulos, Stavros, Galanis, Michalis D., Goutis, Costas E.

“…Coarse grain reconfigurable array architectures have become increasingly popular due to their flexibility, scalability and performance. However, the mapping of…”
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Efficient high-performance implementation of JPEG-LS encoder by Papadonikolakis, Markos E., Kakarountas, Athanasios P., Goutis, Costas E.

“…A new design approach to create an efficient high-performance JPEG-LS encoder is proposed in this paper. The proposed implementation compresses the image data…”
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Evaluation of design alternatives for the 2-D-discrete wavelet transform by Zervas, N.D., Anagnostopoulos, G.P., Spiliotopoulos, V., Andreopoulos, Y., Goutis, C.E.

“…In this paper, the three main hardware architectures for the 2-D discrete wavelet transform (2-D-DWT) are reviewed. Also, optimization techniques applicable to…”
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A Top-Down Design Methodology for Ultrahigh-Performance Hashing Cores by Michail, H.E., Kakarountas, A.P., Milidonis, A.S., Goutis, C.E.

“…Many cryptographic primitives that are used in cryptographic schemes and security protocols such as SET, PKI, IPSec, and VPNs utilize hash functions, which…”
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Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays by Dimitroulakos, Grigorios, Kostaras, Nikos, Galanis, Michalis D., Goutis, Costas E.

“…Coarse Grain Reconfigurable Array (CGRA) architectures have been extensively used for accelerating time consuming loops. The design of such systems requires…”
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High-speed FPGA implementation of secure hash algorithm for IPSec and VPN applications by KAKAROUNTAS, Athanasios P, MICHAIL, Haralambos, MILIDONIS, Athanasios, GOUTIS, Costas E, THEODORIDIS, George

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Design space exploration of an optimized compiler approach for a generic reconfigurable array architecture by DIMITROULAKOS, Grigoris, GALANIS, Michalis D, GOUTIS, Costas E

“…Several mesh-like coarse-grained reconfigurable architectures have been devised in the last few years accompanied with their corresponding mapping flows. One…”
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Decoupled Processors Architecture for Accelerating Data Intensive Applications using Scratch-Pad Memory Hierarchy by Milidonis, Athanasios, Alachiotis, Nikolaos, Porpodas, Vasileios, Michail, Harris, Panagiotakopoulos, Georgios, Kakarountas, Athanasios P., Goutis, Costas E.

“…We present an architecture of decoupled processors with a memory hierarchy consisting only of scratch-pad memories, and a main memory. This architecture…”
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Speedups from extending embedded processors with a high-performance coarse-grained reconfigurable data-path by Galanis, Michalis D., Goutis, Costas E.

“…In this paper, an embedded system that extends microprocessor cores with a high-performance coarse-grained reconfigurable data-path is introduced. The…”
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Performance and Energy Consumption Improvements in Microprocessor Systems Utilizing a Coprocessor Data-Path by Galanis, Michalis D., Dimitroulakos, Gregory, Goutis, Costas E.

“…The speedups and the energy reductions achieved in a generic single-chip microprocessor system by employing a high-performance data-path are presented. The…”
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Partitioning methodology for heterogeneous reconfigurable functional units by GALANIS, Michalis D, DIMITROULAKOS, Gregory, GOUTIS, Costas E

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Speedups and Energy Reductions From Mapping DSP Applications on an Embedded Reconfigurable System by Galanis, M.D., Dimitroulakos, G., Goutis, C.E.

“…This paper presents performance improvements and energy savings from mapping real-world benchmarks on an embedded single-chip platform that includes…”
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Exploring the speedups of embedded microprocessor systems utilizing a high-performance coprocessor data-path by GALANIS, Michalis D, DIMITROULAKOS, Gregory, GOUTIS, Costas E

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Performance improvements from partitioning applications to FPGA hardware in embedded SoCs by GALANIS, Michalis D, DIMITROULAKOS, Gregory, GOUTIS, Costas E

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Memory accesses reordering for interconnect power reduction in sum-of-products computations by Masselos, K., Theoharis, S., Merakos, P., Stouraitis, T., Goutis, C.E.

“…Techniques for interconnect power consumption reduction in realizations of sum-of-products computations are presented. The proposed techniques reorder the…”
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A method for partitioning applications in hybrid reconfigurable architectures by Galanis, Michalis D., Milidonis, Athanasios, Theodoridis, George, Soudris, Dimitrios, Goutis, Costas E.

“…In this paper, we propose a methodology for accelerating application segments by partitioning them between reconfigurable hardware blocks of different…”
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