Search Results - "Goessel, M."

Low cost concurrent error detection for the advanced encryption standard by Wu, K., Ramesh Karri, Kuznetsov, G., Goessel, M.

“…We present a new low-cost concurrent checking method for the advanced encryption standard (AES) encryption algorithm. In this method, the parity of the 128-bit…”
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Checking Combinational Circuits by the Method of Logic Complement by Goessel, M., Morozov, A. V., Sapozhnikov, V. V., Sapozhnikov, Vl. V.

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Diagnosis of scan-chains by use of a configurable signature register and error-correcting codes by Leininger, A., Goessel, M., Muhmenthaler, P.

“…In this paper a new diagnosis method for scan designs with many scan-paths based on error correcting linear block codes with N information bits and K control…”
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Parity-based concurrent error detection in symmetric block ciphers by Karri, R., Kuznetsov, G., Goessel, M.

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Self-checking comparator with one periodic output by Kundu, S., Sogomonyan, E.S., Goessel, M., Tarnick, S.

“…In this paper we propose a new self-checking comparator with one periodic output. The comparator can be used as a two-rail checker or as an equality checker…”
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An interval-based diagnosis scheme for identifying failing vectors in a scan-BIST environment by Chunsheng Liu, Chakrabarty, K., Goessel, M.

“…We present a new scan-BIST approach for determining failing vectors for fault diagnosis. This approach is based on the application of overlapping intervals of…”
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Design of self-testing and on-line fault detection combinational circuits with weakly independent outputs by Sogomonyan, E. S., Goessel, M.

“…In this article we propose a structure dependent method for the systematic design of combinational self-testing fault detection circuits that is well adapted…”
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A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing by Sogomonyan, Es, Singh, Ad, Goessel, M

“…This paper introduces a new multi-mode scannable memory element which allows pseudorandom testing to be integrated with scan in sequential circuits without the…”
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A new method of redundancy addition for circuit optimization by Ocheretnij, V., Saposhnikov, V., Saposhnikov, Vl, Goessel, M.

“…A new method for the optimization of combinational circuits by the addition of redundancy is investigated. In the first step, the original circuit is modified…”
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Experimental Results for Self-Dual Multi-Output Combinational Circuits by Saposhnikov, Vl V, Moshanin, V, Saposhnikov, Vv, Goessel, M

“…In this short note, the possibilities and the limitations for the application of self-dual circuits with alternating inputs are experimentally investigated…”
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Self-dual parity checking-A new method for on-line testing by Saposhnikov, Vl.V., Dmitriev, A., Goessel, M., Saposhnikov, V.V.

“…Self-dual parity checking as a modification of ordinary parity checking is proposed in this paper. This method is based on the newly introduced concept of a…”
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Highly Efficient Test Response Compaction Using a Hierarchical X-Masking Technique by Rabenalt, T., Richter, M., Poehl, F., Goessel, M.

“…This paper presents a highly effective compactor architecture for processing test responses with a high percentage of x-values. The key component is a…”
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A multi-mode scannable memory element for high test application efficiency and delay testing by Sogomonyan, E.S., Singh, A.D., Goessel, M.

“…This paper introduces a new multimode scannable memory element which allows pseudorandom testing to be integrated with scan in sequential circuits without the…”
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Self-dual duplication for error detection by Saposhnikov, Vl.V., Saposhnikov, V.V., Dmitriev, A., Goessel, M.

“…In this paper we propose a new method for the implementation of a self-dual circuit with alternating inputs. For every circuit output the self-dual complement…”
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A New Decoding Method for Double Error Correcting Cross Parity Codes by Duchrau, G., Gossel, M.

“…In this paper a new and simple method for 2-bit error correction for cross parity codes is proposed. All single and double bit errors, concerning data bits,…”
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A new method for concurrent checking by use of a 1-out-of-4 code by Goessel, M., Saposhnikov, Vl, Dmitriev, A., Saposhnikov, V.

“…In this paper a new method for concurrent checking is proposed. For an arbitrarily given combinational circuit f an additional complementary circuit g is…”
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A new 3-bit burst-error correcting code by Klockmann, A., Georgakos, G., Goessel, M.

“…In this paper a new 3-bit burst-error correcting code is proposed. Compared to a 1-bit error correcting Hamming code only two additional check bits are needed…”
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High Performance Compaction for Test Responses with Many Unknowns by Rabenalt, T, Richter, M, Goessel, M

“…We present a new compactor architecture for extreme compaction of test responses with a high percentage of x-values. The test response data is compacted into a…”
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Using timing flexibility of automatic test equipment to complement X-tolerant test compression techniques by Leininger, A., Fischer, M., Richter, M., Goessel, M.

“…This paper introduces the concept of utilizing the timing flexibility of automatic test equipment (ATE) when designing X-tolerant test compactors. Redundant…”
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A Signature Analysis Technique for the Identification of Failing Vectors with Application to Scan-BIST by Goessel, Michael, Chakrabarty, Krishnendu, Ocheretnij, Vitalij, Leininger, Andreas

“…We present a new technique for uniquely identifying a single failing vector in an interval of test vectors. This technique is applicable to combinational…”
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