Search Results - "Goel, Sandeep Kumar"

Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption by Ingelsson, Urban, Goel, Sandeep Kumar, Larsson, Erik, Marinissen, Erik Jan

“…System-on-chips (SOCs) and 3D stacked ICs are often tested for manufacturing defects in a modular fashion, enabling us to record the module test pass…”
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Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study by Goel, Sandeep Kumar, Adham, Saman, Min-Jer Wang, Ji-Jan Chen, Tze-Chiang Huang, Mehta, Ashok, Lee, Frank, Chickermane, Vivek, Keller, Brion, Valind, Thomas, Mukherjee, Subhasish, Sood, Navdeep, Jeongho Cho, Lee, Hayden Hyungdong, Jungi Choi, Sangdoo Kim

“…Recent advances in semiconductor process technology especially interconnects using Through Silicon Vias (TSVs) enable the heterogeneous system integration…”
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DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks by Deutsch, S., Keller, B., Chickermane, V., Mukherjee, S., Sood, N., Goel, S. K., Chen, J., Mehta, A., Lee, F., Marinissen, E. J.

“…Three-dimensional (3D) die stacking is an emerging integration technology which brings benefits with respect to heterogeneous integration, inter-die…”
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Effective and efficient test architecture design for SOCs by Goel, S.K., Marinissen, E.J.

“…This paper deals with the design of test architectures for modular SOC testing. These architectures consist of wrappers and TAMs (test access mechanisms). For…”
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Comparing the effectiveness of deterministic bridge fault and multiple-detect stuck fault patterns for physical bridge defects: A simulation and silicon study by Goel, S.K., Devta-Prasanna, N., Ward, M.

“…Shrinking feature size and increased wire density increase the likelihood of occurrence of bridge related defects. N- detect based pattern sets are used…”
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Core-based scan architecture for silicon debug by Vermeulen, B., Waayers, T., Goel, S.K.

“…In this paper, we present a core-based scan architecture for silicon debug, which is currently being standardized within Philips. The reasons behind the…”
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Innovative Practices Track: Test of 3D ICs & Chiplets by Goel, Sandeep Kumar, Pendharkar, Sandeep, Liu, Chunsheng

“…Author: Sandeep Kumar Goel…”
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A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing by Lin, Mu-Shan, Huang, Tze-Chiang, Tsai, Chien-Chun, Tam, King-Ho, Hsieh, Cheng-Hsiang, Chen, Tom, Huang, Wen-Hung, Hu, Jack, Chen, Yu-Chi, Goel, Sandeep Kumar, Fu, Chin-Ming, Rusu, Stefan, Li, Chao-Chieh, Yang, Sheng-Yao, Wong, Mei, Yang, Shu-Chun, Lee, Frank

“…A dual-chiplet Chip-on-Wafer-on-Substrate (CoWoS ® ) was implemented in 7nm 15M process. Each SoC chiplet has four Arm ® Cortex ® -A72 processors operating at…”
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IEEE P1500-compliant test wrapper design for hierarchical cores by Sehgal, A., Goel, S.K., Marinissen, E.J., Chakrabarty, K.

“…Most system-on-chips (SOCs) today contain hierarchical cores that have multiple levels of design hierarchy. An efficient wrapper design for hierarchical cores…”
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Hierarchical data invalidation analysis for scan-based debug on multiple-clock system chips by Goel, S.K., Vermeulen, B.

“…To debug a digital chip with a scan-based debug methodology, the chip is stopped at a certain point in time in the application. The state of the flip-flops and…”
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Test resource optimization for multi-site testing of SOCs under ATE memory depth constraints by Iyengar, V., Goel, S.K., Marinissen, E.J., Chakrabarty, K.

“…We present a two-step solution to the problem of test resource optimization for multi-site testing of embedded-core-based SOCs. In step 1, an efficient…”
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Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips by Goel, Sandeep Kumar, Vermeulen, Bart

“…Issue Title: Special Issue on the Seventh IEEE European Test Workshop To debug a digital chip with a scan-based debug methodology, the chip is stopped at a…”
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A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation by Chandra, Anshuman, Khan, Moiz, Patidar, Ankita, Takashima, Fumiaki, Goel, Sandeep Kumar, Shankaranarayanan, Bharath, Nguyen, Vuong, Tyagi, Vistrita, Arora, Manish

“…Chip-Iet based multi-die 3DIC design methodology is the paradigm shift in semiconductor manufacturing that enables scalable design integration for SysMoore…”
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A 7-nm 4-GHz Arm^1-Core-Based CoWoS^1 Chiplet Design for High-Performance Computing by Lin, Mu-Shan, Goel, Sandeep Kumar, Fu, Chin-Ming, Rusu, Stefan, Li, Chao-Chieh, Yang, Sheng-Yao, Wong, Mei, Yang, Shu-Chun, Lee, Frank, Huang, Tze-Chiang, Tsai, Chien-Chun, Tam, King-Ho, Hsieh, Kenny Cheng-Hsiang, Chen, Ching-Fang, Huang, Wen-Hung, Hu, Chi-Wei, Chen, Yu-Chi

“…We present a dual-chiplet interposer-based system-in-package (SiP) octo-core processor using Chip-on-Wafer-on-Substrate (CoWoS) technology. Each of the two…”
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Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs by Noia, B., Chakrabarty, K., Goel, S. K., Marinissen, E. J., Verbree, J.

“…Through-silicon via (TSV)-based 3-D stacked ICs (SICs) are becoming increasingly important in the semiconductor industry. In this paper, we address test…”
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A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing by Lin, Mu-Shan, Huang, Tze-Chiang, Tsai, Chien-Chun, Tam, King-Ho, Hsieh, Kenny Cheng-Hsiang, Chen, Ching-Fang, Huang, Wen-Hung, Hu, Chi-Wei, Chen, Yu-Chi, Goel, Sandeep Kumar, Fu, Chin-Ming, Rusu, Stefan, Li, Chao-Chieh, Yang, Sheng-Yao, Wong, Mei, Yang, Shu-Chun, Lee, Frank

“…We present a dual-chiplet interposer-based system-in-package (SiP) octo-core processor using Chip-on-Wafer-on-Substrate (CoWoS) technology. Each of the two…”
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Low-Cost Post-Bond Testing of 3-D ICs Containing a Passive Silicon Interposer Base by Chun-Chuan Chi, Marinissen, Erik Jan, Goel, Sandeep Kumar, Cheng-Wen Wu

“…Through-silicon vias (TSVs) provide high-density vertical interconnects between dies and enable the creation of 3-D ICs having higher performance and lower…”
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Scan Design Using Unsupervised Machine Learning to Reduce Functional Timing and Area Impact by Goel, Sandeep Kumar, Patidar, Ankita, Lee, Frank

“…Scan design adversely affects design performance, including speed, power, and routing congestion. Scan partitioning and reordering are required to mitigate…”
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Efficient observation-point insertion for diagnosability enhancement in digital circuits by Zipeng Li, Goel, Sandeep Kumar, Lee, Frank, Chakrabarty, Krishnendu

“…Chip designers typically do not consider design-for-diagnosis (DfD) for manufacturing defects while implementing an integrated circuit and its design-for-test…”
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Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling by Goel, S., Marinissen, E.J., Sehgal, A., Chakrabarty, K.

“…Many system-on-chip (SOC) integrated circuits today contain hierarchical (parent) cores that have multiple levels of design hierarchy involving "child cores"…”
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