Search Results - "Gössel, Michael"

Modified DEC BCH codes for parallel correction of 3-bit errors comprising a pair of adjacent errors by Badack, Christian, Kern, Thomas, Gössel, Michael

“…In this paper we propose a modification of double error correcting (DEC) BCH codes that allows for a fast correction of arbitrary 1-bit and 2-bit errors, as…”
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Reducing the area overhead of TMR-systems by protecting specific signals by Augustin, Michael, Gössel, Michael, Kraemer, Rolf

“…This paper presents a new method of fault-tolerant design for combinational circuits. For an arbitrary chosen subset X 1 of inputs the designed system is…”
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X-tolerant Test Data Compaction with Accelerated Shift Registers by Hilscher, Martin, Braun, Michael, Richter, Michael, Leininger, Andreas, Gössel, Michael

“…Using the timing flexibility of modern automatic test equipment (ATE) test response data can be compacted without the need for additional X-masking logic. In…”
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Zero-aliasing space compaction of test responses using a single periodic output by Bhattacharya, B.B., Dmitriev, A., Gossel, M.

“…A structure-independent method for space compaction in combinational circuits based on a new generic scheme is presented. It is shown that a single-output…”
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Synthesis of single-output space compactors for scan-based sequential circuits by Bhattacharya, B.B., Dmitriev, A., Gossel, M., Chakrabarty, K.

“…This paper addresses the problem of space compaction of test responses of combinational and scan-based sequential circuits. In a general circuit, compaction of…”
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Accelerated Shift Registers for X-tolerant Test Data Compaction by Hilscher, Martin, Braun, Michael, Richter, Michael, Leininger, Andreas, Gossel, Michael

“…In this paper we present a method for compacting test response data without the need for additional X-masking logic by using the timing flexibility of modern…”
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Implementation of Selective Fault Tolerance with conventional synthesis tools by Augustin, M, Gossel, M, Kraemer, R

“…Circuits implementing the concept of Selective Fault Tolerance according to are fault-tolerant for a specified subset of inputs. In this paper, a new heuristic…”
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Selective fault tolerance for finite state machines by Augustin, M., Gossel, M., Kraemer, R.

“…This paper introduces the concept of Selective Fault Tolerance for sequential circuits. A sequential circuit that is designed according to this method is…”
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Synthesis of single-output space compactors with application to scan-based IP cores by Bhattacharya, Bhargab B., Dmitriev, Alexej, Gössel, Michael, Chakrabarty, Krishendu

“…This paper addresses the problem of space compaction of test responses of combinational and scan-based sequential circuits. It is shown that given a…”
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Doubling Test Cell Throughput by On-Loadboard Hardware- Implementation and Experience in a Production Environment by Faber, F.-U., Beck, M., Barondeau, O., Rabenalt, T., Gossel, M., Leininger, A.

“…This paper reports the experience being made during the implementation of low pin count techniques and their insertion into a production environment. The…”
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On-Line Error Detection for Bit-Serial Multipliers in GF(2m) by Fenn, Sebastian, Gossel, Michael, Benaissa, Mohammed, Taylor, David

“…In this paper error detection is applied to four finite field bit-serial multipliers. It is shown that by using parity prediction, on-line error detection can…”
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Triple error detection for Imai-Kamiyanagi codes based on subsyndrome computations by Badack, Christian, Gossel, Michael

“…Imai-Kamiyanagi codes are a class of linear double error correcting (DEC) codes suitable for fast parallel error correction. The parity-check matrix H' of…”
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Testability evaluation of sequential designs incorporating the multi-mode scannable memory element by Singh, A.D., Sogomonyan, E.S., Gossel, M., Seuring, M.

“…The Multi-Mode Scannable Memory Element (MSME) is a design-for-test technique that combines the testing efficiency of the Circular Self-Test Path approach with…”
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On-line error detection for finite field multipliers by Gossel, M., Fenn, S., Taylor, D.

“…In this paper error-detection is applied to finite field multipliers. It is shown that by using parity prediction, error-detection can be incorporated into…”
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