Search Results - "Gluschenkov, Oleg"
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Energy Density and Temperature Calibration for FEOL Nanosecond Laser Annealing
Published in 2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) (01-08-2020)“…Nanosecond (NLA) laser annealing is under consideration for inclusion into mainstream CMOS technology. Lack of suitable ultra-high speed pyrometery and the…”
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Conference Proceeding -
2
Evolution of Surface Morphology and Strain in Low-Temperature AlN Grown by Plasma-Assisted Molecular Beam Epitaxy
Published in Japanese Journal of Applied Physics (01-03-1998)“…The evolution of stress-driven surface roughening in low-temperature (LT) grown AlN has been investigated in a wide range of film thicknesses using plasma…”
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Journal Article -
3
Advanced BEOL Materials, Processes, and Integration to Reduce Line Resistance of Damascene Cu, Co, and Subtractive Ru Interconnects
Published in 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (12-06-2022)“…Recent progress in materials, processes and integration schemes to reduce line resistance (Line-R) of damascene Cu and alternative conductors (damascene Co and…”
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4
Sub- 10^~\Omega -cm2 n-Type Contact Resistivity for FinFET Technology
Published in IEEE electron device letters (01-11-2016)“…We report record low 8.4 × 10 -10 Ω-cm 2 n-type S/D contact resistivity with laser-induced solid/liquid phase epitaxy of Si:P inside nano-scale contact…”
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Journal Article -
5
Backside Power Distribution for Nanosheet Technologies Beyond 2nm
Published in 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (16-06-2024)“…This paper examines various approaches for integrating backside power distribution network (BSPDN) with nanosheet transistor technologies. Deep Trench Via…”
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6
Dual beam laser annealing for contact resistance reduction and its impact on VLSI integrated circuit variability
Published in 2017 Symposium on VLSI Technology (01-06-2017)“…Introduction of a dual beam (DB) millisecond (mSec) or nanosecond (nSec laser annealing in contact module results in a drastic reduction of contact…”
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7
Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO2 gate dielectrics
Published in IEEE electron device letters (01-05-2003)“…Dependence of CMOS performance on silicon crystal orientation of [100], [111], and [110] has been investigated with the equivalent gate dielectric thickness…”
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Journal Article -
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Improving FinFET Junctions and Contacts via Laser Annealing
Published in 2023 21st International Workshop on Junction Technology (IWJT) (08-06-2023)“…Semiconductor industry transitions from the era of planar FETs to the era of three-dimensional (3D) transistors greatly improving performance per footprint. In…”
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9
Overview of Recent Program on Mechanical Properties of Sea Ice
Published in Journal of cold regions engineering (01-12-1995)“…This paper describes field and laboratory measurements of the evolving physical and mechanical properties of first-year sea ice through a growth season. The…”
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Journal Article -
10
Strained Si Channel MOSFETs with Embedded Silicon Carbon Formed by Solid Phase Epitaxy
Published in 2007 IEEE Symposium on VLSI Technology (01-06-2007)“…Current drive enhancement is demonstrated in sub-40 nm NFETs with strained silicon carbon (Si:C) source and drain using a novel solid-phase epitaxy (SPE)…”
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11
Crystallization of hafnium-oxide-based ferroelectrics for BEOL integration
Published in 2022 6th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) (06-03-2022)“…We review the crystallization of hafnium-oxide-based ferroelectrics intended for back-end-of-line (BEOL) integration. We discuss furnace, rapid thermal, and…”
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12
Development and study of atomic nitrogen sources for synthesis of electronic materials
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Dissertation -
13
External Resistance Reduction by Nanosecond Laser Anneal in Si/SiGe CMOS Technology
Published in 2018 IEEE International Electron Devices Meeting (IEDM) (01-12-2018)“…We report on a significant pFET external resistance reduction (∼40%) and corresponding 10% R ON decrease by nanosecond laser annealing of S/D structures…”
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14
Impact of intra-die thermal variation on accurate MOSFET gate-length measurement
Published in 2009 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (01-05-2009)“…It is known that significant intra-die thermal absorption variation is caused by non-optimized rapid thermal anneal (RTA) conditions and the variation depends…”
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15
Simulation of 3D Doping by Plasma Immersion Ion Implantation for FinFET or deep Trench Doping Applications. Effect of main Process Parameters and Study of Wall Doping Non-Uniformity as Function of Form Factor and Device Scaling
Published in 2018 22nd International Conference on Ion Implantation Technology (IIT) (01-09-2018)“…Understanding and simulating 3D doping performed by Plasma Immersion Ion Implantation on FinFETs or on deep trenches for flash memories or power devices…”
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16
Advanced BEOL Interconnects
Published in 2020 IEEE International Interconnect Technology Conference (IITC) (05-10-2020)“…Feasibility of single damascene Cu BEOL nanowires with TaN/Ta barrier (i.e. omitting a CVD-Co liner) was studied. Successful Cu gap-fill in 36 nm pitch…”
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17
Integrated dual SPE processes with low contact resistivity for future CMOS technologies
Published in 2017 IEEE International Electron Devices Meeting (IEDM) (01-12-2017)“…In this study, a manufacturable CMOS dual solid phase epitaxy (SPE) process with pc <; 2.2×10 -9 Q-cm 2 on both NFET and PFET is demonstrated on the hardware…”
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18
Development and study of atomic nitrogen sources for synthesis of electronic materials
Published 01-01-1999“…Atomic nitrogen production in pure nitrogen discharges is analyzed from the standpoint of developing efficient atomic nitrogen sources for the synthesis of…”
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Dissertation -
19
High Performance 65nm SOI Transistors Using Laser Spike Annealing
Published in 2006 European Solid-State Device Research Conference (01-09-2006)“…In this paper we present enhancements in transistor performance and manufacturability of a high performance 65nm node SOI transistor by the combination of…”
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Conference Proceeding -
20
Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT
Published in 2016 IEEE International Electron Devices Meeting (IEDM) (01-12-2016)“…Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In…”
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Conference Proceeding