Search Results - "Gieser, Horst"

Identification of Soft Failure Mechanisms Triggered by ESD Stress on a Powered USB 3.0 Interface by Koch, Sebastian, Orr, Benjamin J., Gossner, Harald, Gieser, Horst A., Maurer, Linus

“…The objective of this work is to identify electrostatic discharge (ESD) related soft failure mechanisms early in the product life cycle. We compare different…”
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Investigating Profiled Side-Channel Attacks Against the DES Key Schedule by Johann Heyszl, Katja Miller, Florian Unterstein, Marc Schink, Alexander Wagner, Horst Gieser, Sven Freud, Tobias Damm, Dominik Klein, Dennis Kügler

“…Recent publications describe profiled single trace side-channel attacks (SCAs) against the DES key-schedule of a “commercially available security controller”…”
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Verification of physical designs using an integrated reverse engineering flow for nanoscale technologies by Lippmann, Bernhard, Unverricht, Niklas, Singla, Aayush, Ludwig, Matthias, Werner, Michael, Egger, Peter, Duebotzky, Anja, Graeb, Helmut, Gieser, Horst, Rasche, Martin, Kellermann, Oliver

“…Considering the potential risks of piracy and malicious manipulation of complex integrated circuits using worldwide distributed manufacturing sites, an…”
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Physical and Functional Reverse Engineering Challenges for Advanced Semiconductor Solutions by Lippmann, Bernhard, Bette, Ann-Christin, Ludwig, Matthias, Mutter, Johannes, Baehr, Johanna, Hepp, Alexander, Gieser, Horst, Kovac, Nicola, Zweifel, Tobias, Rasche, Martin, Kellermann, Oliver

“…Motivated by the threats of malicious modification and piracy arising from worldwide distributed supply chains, the goal of RESEC is the creation,…”
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Investigating Profiled Side-Channel Attacks Against the DES Key Schedule by Heyszl, Johann, Miller, Katja, Unterstein, Florian, Schink, Marc, Wagner, Alexander, Gieser, Horst, Freud, Sven, Damm, Tobias, Klein, Dominik, Kügler, Dennis

“…Recent publications describe profiled single trace side-channel attacks (SCAs) against the DES key-schedule of a “commercially available security controller”…”
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ESD performance evaluation of powered high-speed interfaces by Koch, Sebastian, Gossner, Harald, Gieser, Horst, Maurer, Linus

“…An approach towards evaluating the ESD performance of high-speed interfaces is presented. By applying ESD stress to powered USB 3.0 interfaces the propagation…”
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In-situ ESD current sensing in a pick and place machine by Jirutkova, Ellen, Wolf, Heinrich, Gieser, Horst

“…This paper presents a method to measure current discharge directly in an assembly machine. Pre-tests with a multi-purpose current monitor are performed to show…”
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Very fast transmission line pulsing of integrated structures and the charged device model by Gieser, Horst, Haunschild, Markus

“…Transmission line pulsing (TLP) is well-established for the IV-characterization of electrostatic discharge (ESD)-protection elements. There still is a…”
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Investigating the CDM susceptibility of IC’s at package and wafer level by capacitive coupled TLP by Wolf, Heinrich, Gieser, Horst, Walter, Dirk

“…The method of the capacitive coupled transmission line pulsing (CC-TLP) is applied to a product IC at package level and for the first time at wafer level. The…”
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Towards a Comprehensive System for Physical Hardware Inspection for Trust by Lippmann, Bernhard, Ludwig, Matthias, Houdeau, Detlef, Kovac, Nicola, Gieser, Horst

“…The US National Cybersecurity Strategy asks for "securing the semiconductor supply chain" [1], and the EU Chips Act addresses the "tech sovereignty" [2]. Both…”
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System Level ESD Testing with Capacitively Coupled Stress Pulses by Jirutkova, Ellen, Wolf, Heinrich, Weber, Johannes, Gieser, Horst

“…A debugging test method is presented which helps to identify susceptible pins which failed after system level ESD testing in compliance with IEC 61000-4-2. It…”
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Secondary discharge - A potential risk during system level ESD testing by Wolf, Heinrich, Gieser, Horst

“…By means of a floating handheld electronic product this work describes the influence of secondary discharge events during system level ESD testing on the…”
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ESD Susceptibility of Submicron Air Gaps by Wolf, Heinrich, Gieser, Horst, Bonfert, Detlef, Hauser, Markus

“…This work describes the investigation of the ESD susceptibility of submicron air gaps which are used e.g. in filter devices. The breakdown behaviour of the air…”
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Stress Current Slew Rate Sensitivity of an Ultra-High-Speed Interface IC by Weber, Johannes, Fung, Rita, Wong, Richard, Wolf, Heinrich, Gieser, Horst A., Maurer, Linus

“…This study analyzes the Electrostatic Discharge (ESD) susceptibility of a 28nm high-speed CMOS Integrated Circuit (IC) for network applications (25Gbps),…”
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Investigating the CDM susceptibility of IC's at package and wafer level by capacitive coupled TLP : Electrostatic Discharge Reliability by WOLF, Heinrich, GIESER, Horst, WALTER, Dirk

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On-chip electrostatic discharge ESD by Gieser, Horst A.

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Survey on Very Fast TLP and Ultra Fast Repetitive Pulsing for Characterization in the CDM-Domain by Gieser, H.A., Wolf, H.

“…Charged device model pulses may be less than 1 ns wide with peak currents exceeding 10 A. They are a true challenge for the ESD protection of advanced…”
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Advanced integration technology for fabricating high-speed electro-optical sub-assembly by Palavesam, Nagarajan, Choi, Jung Han, Hell, Waltraud, Fiol, Gerrit, Velthaus, Karl-Otto, Zerna, Conrad, Gieser, Horst, Landesberger, Christof

“…Here, we report flip-chip bonding processes based on Anisotropic Conductive Film (ACF) and Sn-Ag-Cu (SAC) solder implemented for bonding three test chips (two…”
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Integrated Flow for Reverse Engineering of Nanoscale Technologies by Lippmann, Bernhard, Werner, Michael, Unverricht, Niklas, Singla, Aayush, Egger, Peter, Dubotzky, Anja, Gieser, Horst, Rasche, Martin, Kellermann, Oliver, Graeb, Helmut

“…In view of potential risks of piracy and malicious manipulation of complex integrated circuits built in technologies of 45 nm and less, there is an increasing…”
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Capacitively coupled transmission line pulsing cc-TLP––a traceable and reproducible stress method in the CDM-domain by Wolf, Heinrich, Gieser, Horst, Stadler, Wolfgang, Wilkening, Wolfgang

“…This paper describes a new test method called capacitively coupled transmission line pulsing cc-TLP. It is applied to different test circuits which were…”
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