Search Results - "Gia Vinh Luong"

Benchmarking of Homojunction Strained-Si NW Tunnel FETs for Basic Analog Functions by Biswas, Arnab, Gia Vinh Luong, Chowdhury, M. Foysol, Alper, Cem, Qing-Tai Zhao, Udrea, Florin, Mantl, Siegfried, Ionescu, Adrian M.

“…This paper reports a compact ambipolar model for homojunction strained-silicon (sSi) nanowire (NW) tunnel FETs (TFETs) capable of accurately describing both…”
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Strained Si and SiGe Nanowire Tunnel FETs for Logic and Analog Applications by Qing-Tai Zhao, Richter, Simon, Schulte-Braucks, Christian, Knoll, Lars, Blaeser, Sebastian, Gia Vinh Luong, Trellenkamp, Stefan, Schafer, Anna, Tiedemann, Andreas, Hartmann, Jean-Michel, Bourdelle, Konstantin, Mantl, Siegfried

“…Guided by the Wentzel-Kramers-Brillouin approximation for band-to-band tunneling (BTBT), various performance boosters for Si TFETs are presented and…”
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Experimental I – V(T) and C – V Analysis of Si Planar p-TFETs on Ultrathin Body by Chang Liu, Qinghua Han, Glass, Stefan, Gia Vinh Luong, Narimani, Keyvan, Tiedemann, Andreas T., Fox, Alfred, Wenjie Yu, Xi Wang, Mantl, Siegfried, Qing-Tai Zhao

“…We present the experimental analysis of planar Si p-tunnel FETs (TFETs) fabricated on ultrathin body Silicon on Insulator (SOI) substrates by an optimized…”
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Experimental Investigation of – Characteristics of Si Tunnel FETs by Chang Liu, Glass, Stefan, Gia Vinh Luong, Narimani, Keyvan, Qinghua Han, Tiedemann, Andreas T., Fox, Alfred, Wenjie Yu, Xi Wang, Mantl, Siegfried, Qing-Tai Zhao

“…This letter presents an experimental capacitance-voltage C-V analysis for Si p-tunnel FETs (TFETs) fabricated on ultrathin body at various frequencies and…”
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Implementation of a DC compact model for double-gate Tunnel-FET based on 2D calculations and application in circuit simulation by Horst, Fabian, Graef, Michael, Hosenfeld, Fabian, Farokhnejad, Atieh, Hain, Franziska, Gia Vinh Luong, Qing-Tai Zhao, Iniguez, Benjamin, Kloes, Alexander

“…This paper introduces a two-dimensional physics-based compact model for a double-gate (DG) Tunnel-FET (TFET) implemented in Verilog-A. The compact model is…”
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Si n-TFETs on ultra thin body with suppressed ambipolarity by Chang Liu, Qinghua Han, Luong, Gia Vinh, Narimani, Keyvan, Glass, Stefan, Tiedemann, Andreas T., Trellenkamp, Stefan, Wenjie Yu, Xi Wang, Mantl, Siegfried, Qing-Tai Zhao

“…This paper presents an ultra thin body Si n-TFET which exploits a multi-finger gate layout and steep junction formed by dopant implantation into silicide (IIS)…”
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Static noise margin analysis of 8T TFET SRAM cells using a 2D compact model adapted to measurement data of fabricated TFET devices by Horst, Fabian, Graef, Michael, Hosenfeld, Fabian, Farokhnejad, Atieh, Gia Vinh Luong, Qing-Tai Zhao, Iniguez, Benjamin, Kloes, Alexander

“…In this paper a static noise margin (SNM) analysis is done for an 8T SRAM cell build up with complementary tunnel-FETs (TFETs). The simulations are done with…”
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Strained silicon nanowire tunnel FETs and NAND logic by Qing-Tai Zhao, Knoll, Lars, Richter, Simon, Schulte-Braucks, Christian, Gia Vinh Luong, Blaser, Sebastian, Schafer, Anna, Trellenkamp, Stefan, Mantl, Siegfried

“…We present strained Si TFETs with different architectures, from planar to highly down scaled gate all around (GAA) nanowire (NW) devices. Optimizing the TFET…”
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Experimental demonstration of inverter and NAND operation in p-TFET logic at ultra-low supply voltages down to VDD = 0.15 V by Richter, Simon, Schulte-Braucks, Christian, Knoll, Lars, Luong, Gia Vinh, Schafer, Anna, Trellenkamp, Stefan, Qing-Tai Zhao, Mantl, Siegfried

“…Tunnel-FETs (TFETs) have been studied extensively as a replacement for MOSFETs in the supply voltage regime below V DD = 0.3 V [1]. Due to the TFET ability for…”
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DC/AC Compact Modeling of TFETs for Circuit Simulation of Logic Cells Based on an Analytical Physics-Based Framework by Horst, Fabian, Kloes, Alexander, Farokhnejad, Atieh, Graef, Michael, Hosenfeld, Fabian, Luong, Gia Vinh, Liu, Chang, Zhao, Qing-Tai, Lime, Francois, Iniguez, Benjamin

“…This paper presents a DC/AC compact model for double-gate (DG) tunnel field-effect transistors (TFET) which is based on a unified analytical modeling…”
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