Search Results - "Ghai, Dhruva"

Process Variation Analysis and Optimization of a FinFET-Based VCO by Yanambaka, Venkata P., Mohanty, Saraju P., Kougianos, Elias, Ghai, Dhruva, Ghai, Garima

“…Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS for nanoscale technologies. In this paper, the viability of a mixed-signal…”
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A Neighbor Trust-Based Mechanism to Protect Mobile Networks by Vaseer, Gurveen, Ghai, Garima, Ghai, Dhruva, Patheja, Pushpinder S.

“…Mobile nodes in a mobile ad hoc network (MANET) form a temporal link between a sender and receiver due to their continuous movement in a limited area. This…”
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Comparative analysis of double gate FinFET configurations for analog circuit design by Ghai, Dhruva, Mohanty, Saraju P., Thakral, Garima

“…FinFETs are being adopted as an alternative to nanoscale classical MOSFET for digital circuits. The double-gate (DG) FinFET gives rise to a rich design space…”
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Design of Parasitic and Process-Variation Aware Nano-CMOS RF Circuits: A VCO Case Study by Ghai, D., Mohanty, S.P., Kougianos, E.

“…This paper proposes a novel flow for parasitic and process-variation aware design of radio-frequency integrated circuits (RFICs). A nano-CMOS current-starved…”
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Double gate FinFET based mixed-signal design: A VCO case study by Ghai, Dhruva, Mohanty, Saraju P., Thakral, Garima

“…This paper investigates mixed-signal design for double-gate (DG) FinFET technology using a current-starved voltage controlled oscillator (VCO) as a case study…”
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Distributed Trust-Based Multiple Attack Prevention for Secure MANETs by Vaseer, Gurveen, Ghai, Garima, Ghai, Dhruva

“…Mobile ad hoc networks (MANETs) are self-configuring, dynamic networks in which nodes are free to move. These nodes are susceptible to various malicious…”
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Message from the General Chairs

“…Presents the introductory welcome message from the conference proceedings. May include the conference officers' congratulations to all involved with the…”
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Message from the General Chairs

“…Presents the introductory welcome message from the conference proceedings. May include the conference officers' congratulations to all involved with the…”
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A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM by Thakral, G., Mohanty, S.P., Ghai, D., Pradhan, D.K.

“…A novel design approach for simultaneous power and stability (static noise margin, SNM) optimization of nano-CMOS static random access memory (SRAM) is…”
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A P4VT (Power Performance Process Parasitic Voltage Temperature) Aware Dual-VTh Nano-CMOS VCO by Mohanty, S.P., Ghai, D., Kougianos, E.

“…We present the design flow for a P4VT (power-performance-process-parasitic-voltage-temperature) aware voltage controlled oscillator (VCO). Through simulations,…”
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A combined packet classifier and scheduler towards Net-Centric Multimedia Processor design by Mohanty, S.P., Ghai, D., Kougianos, E., Patra, P.

“…We introduce a net-centric multimedia processor (NMP) with built-in digital rights management (DRM) facilities to facilitate Internet protocol packet…”
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Variability-aware low -power techniques for nanoscale mixed-signal circuits by Ghai, Dhruva V

“…New circuit design techniques that accommodate lower supply voltages necessary for portable systems need to be integrated into the semiconductor intellectual…”
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Fast optimization of nano-CMOS voltage-controlled oscillator using polynomial regression and genetic algorithm by Ghai, Dhruva, Mohanty, Saraju P., Thakral, Garima

“…Fast optimization of CMOS circuits is needed to reduce design cycle time and chip cost and to enhance yield. Mature electronic design automation (EDA) tools…”
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Variability-aware low -power techniques for nanoscale mixed-signal circuits by Ghai, Dhruva V

“…New circuit design techniques that accommodate lower supply voltages necessary for portable systems need to be integrated into the semiconductor intellectual…”
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Fast analog design optimization using regression-based modeling and genetic algorithm: A nano-CMOS VCO case study by Ghai, D., Mohanty, S. P., Thakral, G.

“…The mature electronic design automation (EDA) tools and well-defined abstraction-levels for digital circuits have almost automated the digital design process…”
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A PVT aware accurate statistical logic library for high-κ metal-gate nano-CMOS by Ghai, Dhruva, Mohanty, Saraju P., Kougianos, Elias, Patra, Priyadarsan

“…The semiconductor industry is headed towards a new era of scaling and uncertainty with new key building blocks for the next-generation chips, the high-kappa…”
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P3 (power-performance-process) optimization of nano-CMOS SRAMusing statistical DOE-ILP by Thakral, Garima, Mohanty, Saraju P, Ghai, Dhruva, Pradhan, Dhiraj K

“…In this paper, a novel design flow is presented for simultaneous P3 (power minimization, performance maximization and process variation tolerance) optimization…”
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A universal level converter towards the realization of energy efficient implantable drug delivery Nano-Electro-Mechanical-Systems by Mohanty, Saraju P., Ghai, Dhruva, Kougianos, Elias, Joshi, Bharat

“…Nano-Electro-Mechanical-Systems (NEMS) are a technological solution for building miniature systems which can be beneficial in terms of safety, efficacy, or…”
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Computing in Geographic Information Systems [Book Review] by Ghai, Dhruva

“…Recently, geographic information systems (GISs) have received much attention for applications in smart cities, accomplishing tasks including determining how…”
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Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design by Ghai, D., Mohanty, S.P., Kougianos, E.

“…In this paper we present a parasitic aware, process variation tolerant optimization methodology that may be applied to nanoscale circuits to ensure better…”
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