Search Results - "Garros, Xavier"

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  1. 1

    A Complete Characterization and Modeling of the BTI-Induced Dynamic Variability of SRAM Arrays in 28-nm FD-SOI Technology by El Husseini, Joanna, Garros, Xavier, Cluzel, Jacques, Subirats, Alexandre, Makosiej, Adam, Weber, Olivier, Thomas, Olivier, Huard, Vincent, Federspiel, Xavier, Reimbold, Gilles

    Published in IEEE transactions on electron devices (01-12-2014)
    “…In this paper, we present for the first time a direct measurement procedure to characterize the bias temperature instability (BTI)-induced dynamic variability…”
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    Journal Article
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    Frequency characterization and modeling of interface traps in HfSixOy/HfO2 gate dielectric stack from a capacitance point-of-view by Masson, Pascal, Autran, Jean-Luc, Houssa, Michel, Garros, Xavier, Leroux, Charles

    Published in Applied physics letters (28-10-2002)
    “…A time-resolved analysis of the capacitance–voltage (C–V) technique and an inverse modeling approach have been developed to determine the energy distribution…”
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    Journal Article
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    A New Direct Measurement Method of Time Dependent Dielectric Breakdown at High Frequency by Arabi, Melissa, Garros, Xavier, Cluzel, Jacques, Rafik, Mustapha, Federspiel, Xavier, Ghibaudo, Gerard

    Published in IEEE electron device letters (01-10-2020)
    “…A novel technique is presented for a direct evaluation of oxide breakdown under AC stress at high frequencies up to 500MHz. It relies on a RF setup, which…”
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    Journal Article
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    Characterization and modeling of dynamic variability induced by BTI in nano-scaled transistors by Garros, Xavier, Laurent, Antoine, Subirats, Alexandre, Federspiel, X., Vincent, E., Reimbold, Gilles

    Published in Microelectronics and reliability (01-01-2018)
    “…In this paper, dynamic variability (DV) induced by BTI is deeply investigated in nano-scaled devices by means of statistical measurements and modeling. The…”
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    Journal Article
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    Impact of gate impedance on dielectric breakdown evaluation for 28 nm FDSOI transistors by Diab, Amer, Garros, Xavier, Rafik, Mustapha, Federspiel, Xavier, Vincent, Emmanuel, Reimbold, Gilles

    Published in Microelectronic engineering (25-06-2017)
    “…In this paper, we studied the influence of adding gate impedance (Rg) on the breakdown reliability of 28 nm Fully-Depleted Silicon-On-Insulator (FDSOI)…”
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    Journal Article
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    Impact of gate impedance on dielectric breakdown evaluation for 28nm FDSOI transistors by Diab, Amer, Garros, Xavier, Rafik, Mustapha, Federspiel, Xavier, Vincent, Emmanuel, Reimbold, Gilles

    Published in Microelectronic engineering (25-06-2017)
    “…In this paper, we studied the influence of adding gate impedance (Rg) on the breakdown reliability of 28nm Fully-Depleted Silicon-On-Insulator (FDSOI)…”
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    Journal Article
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    Modeling the Dynamic Variability Induced by Charged Traps in a Bilayer Gate Oxide by Subirats, Alexandre, Garros, Xavier, El Husseini, Joanna, Vincent, Emmanuel, Reimbold, Gilles, Ghibaudo, Gerard

    Published in IEEE transactions on electron devices (01-02-2015)
    “…In this paper, we revisit the classic single layer defect centric model (DCM), largely used in reliability studies, in the more realistic case of bilayer gate…”
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    Journal Article
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    Impact of Single Charge Trapping on the Variability of Ultrascaled Planar and Trigate FDSOI MOSFETs: Experiment Versus Simulation by Subirats, Alexandre, Garros, Xavier, El Husseini, Joanna, Le Royer, Cyrille, Reimbold, Gilles, Ghibaudo, Gerard

    Published in IEEE transactions on electron devices (01-08-2013)
    “…The impact of single charge trapping on the threshold voltage Vt of ultrascaled fully depleted silicon-on-insulator transistors is investigated through dynamic…”
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    Journal Article
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    Fast Measurement of BTI on 28nm Fully Depleted Silicon-On-Insulator MOSFETs at Cryogenic Temperature down to 4K by Contamin, Lauriane, Casse, Mikael, Garros, Xavier, Gaillard, Fred, Vinet, Maud, Galy, Philippe, Juge, Andre, Vincent, Emmanuel, de Franceschi, Silvano, Meunier, Tristan

    “…We report preliminary results on bias temperature instabilities (BTI) on 28FDSOI MOS transistors from 300K to 4K with ultra-fast measurements. Common models…”
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    Conference Proceeding
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    A Methodology to Address RF Aging of 40nm CMOS PA Cells Under 5G mmW Modulation Profiles by Divay, A., Dehos, C., Charlet, I., Gaillard, F., Duriez, B., Garros, X., Antonijevic, J., Hai, J., Revil, N., Forest, J., Knopik, V., Cacho, F., Roy, D., Federspiel, X., Cremer, S., Chevalier, P.

    “…A simplified methodology to link CW (Continuous Wave) RF stresses to complex mission profiles is presented in order to compare the lifetimes of different 40nm…”
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    Conference Proceeding
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    New insight on the geometry dependence of BTI in 3D technologies based on experiments and modeling by Garros, Xavier, Laurent, Antoine, Barraud, Sylvain, Lacord, J., Faynot, Olivier, Ghibaudo, Gerard, Reimbold, Gilles

    Published in 2017 Symposium on VLSI Technology (01-06-2017)
    “…In this paper we deeply investigate the dependence of BTI with transistor scaling. Unlike PBTI, NBTI is strongly enhanced in narrow devices like Nanowire or…”
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    Conference Proceeding
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    Ultra-fast CV methods (< 10µs) for interface trap spectroscopy and BTI reliability characterization using MOS capacitors by Frutuoso, T. Mota, Garros, X., Lugo-Alvarez, J., Kammeugne, R. K., Zouknak, L. D. M., Viey, A., Vandendeale, W., Ferrari, P., Gaillard, F.

    “…Two Ultra-Fast capacitance characterization methods based on the displacement current measure are explored for MOS capacitance devices. The first method…”
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    Conference Proceeding
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    Noise-induced dynamic variability in nano-scale CMOS SRAM cells by Theodorou, Christoforos G., Fadlallah, Mouenes, Garros, Xavier, Dimitriadis, Charalabos, Ghibaudo, Gerard

    “…The lack of dynamic stability in memory circuits such as the Static Random Access Memory can lead to read/write failures or power supply limitations. In this…”
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    Conference Proceeding
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    Precise EOT regrowth extraction enabling performance analysis of low temperature extension first devices by Micout, J., Rafhay, Q., Garros, X., Casse, M., Coignus, J., Pasini, L., Lu, C.-M V., Rambal, N., Fenouillet-Beranger, C., Brunet, L., Romano, G., Gassilloud, R., Batude, P., Vinet, M., Ghibaudo, G.

    “…3D sequential integration requires top FETs processing with a low thermal budget (500°C). The analysis of the origin of the performance difference between Low…”
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    Conference Proceeding
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    CMOS VT characterization by capacitance measurements in FDSOI PIN gated diodes by Navarro, Carlos, Bawedin, Maryline, Andrieu, Francois, Cluzel, Jacques, Garros, Xavier, Cristoloveanu, Sorin

    “…We present a powerful technique for the characterization of FDSOI devices. For example, in CMOS designs, the evaluation of threshold voltage for N and also…”
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    Conference Proceeding
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    Multi-Channel Field-Effect Transistor (MCFET)-Part II: Analysis of Gate Stack and Series Resistance Influence on the MCFET Performance by Bernard, E., Ernst, T., Guillaumot, B., Vulliet, N., Garros, X., Coronel, P., Skotnicki, T., Deleonibus, S., Faynot, O.

    Published in IEEE transactions on electron devices (01-06-2009)
    “…Three-dimensional multi-channel field-effect transistor (MCFET) gate stack and series resistance are investigated and optimized by specifically developed…”
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    Journal Article
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