Search Results - "Gamiz, F"
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Mechanical and thermal properties of graphene modified asphalt binders
Published in Construction & building materials (20-08-2018)“…•Graphene produces a more elastic response in asphalt binders.•Elastomers provide a more effective recovery capacity than graphene.•Graphene reduces the…”
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2
Sequential treadmill exercise and cognitive training synergistically increase adult hippocampal neurogenesis in mice
Published in Physiology & behavior (01-07-2023)“…•Sequential physical and cognitive training has synergic effects on adult neurogenesis.•Physical exercise acutely increases hippocampal cell…”
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3
Impact of Asymmetric Configurations on the Heterogate Germanium Electron-Hole Bilayer Tunnel FET Including Quantum Confinement
Published in IEEE transactions on electron devices (01-11-2015)“…We investigate the effect of asymmetric configurations on the heterogate germanium electron-hole bilayer tunnel FET (TFET) and assess the improvement that they…”
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4
A Simple Approach to Quantum Confinement in Tunneling Field-Effect Transistors
Published in IEEE electron device letters (01-10-2012)“…We present an approach to account for quantum confinement in tunneling field-effect transistors (TFETs) based on the use of a nonlocal band-to-band tunneling…”
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5
Improved Retention Characteristics of Z2-FET Employing Half Back-Gate Control
Published in IEEE transactions on electron devices (01-03-2021)“…The structure of zero impact ionization, zero subthreshold swing field-effect transistor (Z 2 -FET) has been modified by stacking a half side of back-gate (BG)…”
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Thorough Understanding of Retention Time of Z2FET Memory Operation
Published in IEEE transactions on electron devices (01-01-2019)“…A recently reported zero impact ionization and zero subthreshold swing device Z2FET is a promising candidate for capacitor-less dynamic random access memory…”
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Comment on "Optimization of a Pocketed Dual-Metal-Gate TFET by Means of TCAD Simulations Accounting for Quantization-Induced Bandgap Widening"
Published in IEEE transactions on electron devices (01-12-2016)“…In this comment, we assess the validity of the simulation approach implemented by Beneventi et al. to account for the effects of subband discretization of…”
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8
3-D TCAD Study of the Implications of Channel Width and Interface States on FD-SOI Z2-FETs
Published in IEEE transactions on electron devices (01-06-2019)“…3-D numerical technology computer-aided design simulations, based on experimental results, are performed to study the origin of the large Z 2 -FET dynamic…”
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9
Memory Operations of Zero Impact Ionization, Zero Subthreshold Swing FET Matrix Without Selectors
Published in IEEE electron device letters (01-03-2020)“…This work experimentally demonstrates the memory operations of a Z 2 -FET (Zero impact ionization, Zero subthreshold swing) matrix without the use of…”
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10
Effect of confined acoustic phonons on the electron mobility of rectangular nanowires
Published in Applied physics letters (14-10-2013)“…In this paper, we assess the impact of the confined acoustic phonon boundary conditions on the electron mobility of semiconductor nanowires. Specifically, we…”
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11
Memory Operation of Z²-FET Without Selector at High Temperature
Published in IEEE journal of the Electron Devices Society (2021)“…The electrical performance of Z 2 -FET and memory operations of matrix are demonstrated at high temperatures up to 125 °C. The sharp subthreshold slope is…”
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12
A-RAM Memory Cell: Concept and Operation
Published in IEEE electron device letters (01-09-2010)“…Capacitorless single-transistor (1T) DRAM cells are envisioned for replacing the conventional DRAMs where the storage capacitor can hardly be further…”
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13
A new characterization technique for SOI wafers: Split C(V) in pseudo-MOSFET configuration
Published in Solid-state electronics (01-12-2013)“…► Implementation of a novel characterization technique for bare SOI, based on split C-V measurement using pseudo-MOSFET. ► The effective mobility of electrons…”
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Journal Article Conference Proceeding -
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Analytic Potential and Charge Model of Semiconductor Quantum Wells
Published in IEEE transactions on electron devices (01-12-2015)“…An analytical model is proposed to determine the potential and the electron concentration in 1D-confined quantum-well structures. This model is applicable to…”
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Ethics of care: Assessment of the ethical issues in the protocols or consensuses on mechanical restraint in force in Spain
Published in Journal of healthcare quality research (01-05-2024)“…Mechanical restraints are widely used in health care practice, despite the numerous ethical conflicts they raise. The aim of this study is to evaluate the…”
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Multi-Subband Monte Carlo study of device orientation effects in ultra-short channel DGSOI
Published in Solid-state electronics (01-02-2010)“…State-of-the-Art devices in mass production are approaching to the performance limit of traditional MOSFET as the critical dimensions are shrunk. Multi-gate…”
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17
Taste and olfactory status in a gourmand with a right amygdala lesion
Published in Neurocase (04-07-2014)“…In a patient with a lesion of the right amygdala and temporal pole who had the characteristics of the gourmand syndrome, sensory and hedonic testing was…”
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Simulation of Fabricated 20-nm Schottky Barrier MOSFETs on SOI: Impact of Barrier Lowering
Published in IEEE transactions on electron devices (01-05-2012)“…In this paper, we develop a procedure to include in device simulators the barrier lowering (BL) effects that appear in the drain and source contacts of…”
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Modeling the Centroid and the Inversion Charge in Cylindrical Surrounding Gate MOSFETs, Including Quantum Effects
Published in IEEE transactions on electron devices (01-01-2008)“…A semiempirical model was developed for calculating the inversion charge of cylindrical surrounding gate transistors (SGTs), including quantum effects. To…”
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Journal Article -
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Revisited Pseudo-MOSFET Models for the Characterization of Ultrathin SOI Wafers
Published in IEEE transactions on electron devices (01-07-2009)“…The pseudo-MOS transistor (Psi-MOSFET characteristics) is a simple and successful technique for the monitoring of silicon-on-insulator (SOI) wafer quality. To…”
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