Search Results - "Galy, P."

Trap Recovery by in-Situ Annealing in Fully-Depleted MOSFET With Active Silicide Resistor by Amor, S., Kilchytska, V., Flandre, D., Galy, P.

“…This work reports first original results on the impact of active in-situ electro-thermal recovery, on the electrical and low-frequency noise characteristics of…”
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Cryogenic Subthreshold Swing Saturation in FD-SOI MOSFETs Described With Band Broadening by Bohuslavskyi, H., Jansen, A. G. M., Barraud, S., Barral, V., Casse, M., Le Guevel, L., Jehl, X., Hutin, L., Bertrand, B., Billiot, G., Pillonnet, G., Arnaud, F., Galy, P., De Franceschi, S., Vinet, M., Sanquer, M.

“…In the standard MOSFET description of the drain current <inline-formula> <tex-math notation="LaTeX"> {I}_{{D}} </tex-math></inline-formula> as a function of…”
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Cryogenic Temperature Characterization of a 28-nm FD-SOI Dedicated Structure for Advanced CMOS and Quantum Technologies Co-Integration by Galy, P., Camirand Lemyre, J., Lemieux, P., Arnaud, F., Drouin, D., Pioro-Ladriere, Michel

“…Silicon co-integration offers compelling scale-up opportunities for quantum computing. In this framework, cryogenic temperature is required for the coherence…”
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Improved Retention Characteristics of Z2-FET Employing Half Back-Gate Control by Kwon, S., Navarro, C., Gamiz, F., Galy, P., Cristoloveanu, S., Kim, Y. -T., Ahn, J.

“…The structure of zero impact ionization, zero subthreshold swing field-effect transistor (Z 2 -FET) has been modified by stacking a half side of back-gate (BG)…”
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3-D TCAD Study of the Implications of Channel Width and Interface States on FD-SOI Z2-FETs by Navarro, C., Navarro, S., Marquez, C., Padilla, J. L., Galy, P., Gamiz, F.

“…3-D numerical technology computer-aided design simulations, based on experimental results, are performed to study the origin of the large Z 2 -FET dynamic…”
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Memory Operations of Zero Impact Ionization, Zero Subthreshold Swing FET Matrix Without Selectors by Kwon, S., Navarro, C., Galy, P., Cristoloveanu, S., Gamiz, F., Ahn, J., Kim, Y.-T.

“…This work experimentally demonstrates the memory operations of a Z 2 -FET (Zero impact ionization, Zero subthreshold swing) matrix without the use of…”
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Cryogenic Characterization of 28-nm FD-SOI Ring Oscillators With Energy Efficiency Optimization by Bohuslavskyi, H., Barraud, S., Barral, V., Casse, M., Le Guevel, L., Hutin, L., Bertrand, B., Crippa, A., Jehl, X., Pillonnet, G., Jansen, A. G. M., Arnaud, F., Galy, P., Maurand, R., De Franceschi, S., Sanquer, M., Vinet, M.

“…Extensive electrical characterization of ring oscillators (ROs) made in high-<inline-formula> <tex-math notation="LaTeX">{k} </tex-math></inline-formula> metal…”
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Effects of Solanum tuberosum L. ointment on second-degree burns in mice by Silva-Correa, Carmen R, Rosas-Cruz, Galy P, Calderón-Peña, Abhel A, Torre, Víctor E Villarreal-La, Aspajo-Villalaz, Cinthya L, Castañeda-Carranza, Julio A, Dionicio-Rosado, Deivy Y, Gómez-Arce, Ricardo M, Rodríguez-Silva, Cristhian N, Rosario-Chávarri, Jorge Del, Cruzado-Razco, José L

“…Potato ( L.) is mainly characterized by its antioxidant and healing properties. Therefore, this study aimed to evaluate the effects of an ointment based on L…”
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Variability Evaluation of 28nm FD-SOI Technology at Cryogenic Temperatures down to 100mK for Quantum Computing by Paz, B. Cardoso, Le Guevel, L., Casse, M., Billiot, G., Pillonnet, G., Jansen, A. G. M., Maurand, R., Haendler, S., Juge, A., Vincent, E., Galy, P., Ghibaudo, G., Vinet, M., de Franceschi, S., Meunier, T., Gaillard, F.

“…Variability of28nm FD-SOI transistors is evaluated for the first time down to ultra low temperatures (UL T), at T= 1 00mK. High performance is achieved at UL T…”
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Temperature and Gate Leakage Influence on the Z2-FET Memory Operation by Marquez, C., Navarro, S., Navarro, C., Salazar, N., Galy, P., Cristoloveanu, S., Gamiz, F.

“…Advanced 28 nm node FD-SOI Z 2 -FETs with thin top-gate insulator are characterized as capacitor-less DRAM cells. Experimental and 2D-TCAD results demonstrate…”
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Novel tetra-acridine derivatives as dual inhibitors of topoisomerase II and the human proteasome by Vispé, S., Vandenberghe, I., Robin, M., Annereau, J.P., Créancier, L., Pique, V., Galy, J.P., Kruczynski, A., Barret, J.M., Bailly, C.

“…Acridine derivatives, such as amsacrine, represent a well known class of multi-targeted anti-cancer agents that generally interfere with DNA synthesis and…”
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A full characterization of single pitch IO ESD protection based on silicon controlled rectifier and dynamic trigger circuit in CMOS 32 nm node by BOURGEAT, J, GALY, P, DRAY, A, JIMENEZ, J, MARIN-CUDRAZ, D, JACQUIER, B

“…The reliability of electronic devices against electrostatic discharge stresses is still a severe challenge, particularly for deep sub-micron technologies such…”
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Evaluation of the ESD performance of local protections based on SCR or bi-SCR with dynamic or static trigger circuit in 32 nm by Bourgeat, J., Entringer, C., Galy, P., Bafleur, M., Marin-Cudraz, D.

“…The reliability of electronic devices against electrostatic discharge stresses is still a severe challenge, particularly for deep sub-micron technologies such…”
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Beta-Matrix ESD network: Throughout end of placement rules? by Bourgeat, J, Galy, P, Jacquier, B

“…Electrostatic Discharge (ESD) protection for advanced CMOS technologies is based on efficient device Network. But these protection strategies imply some…”
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Comparison between isolated SCR & embedded dual isolated SCR power devices for ESD power clamp in C45nm CMOS technology by Galy, P, Bourgeat, J, Jimenez, J, Entringer, C, Dray, A, Jacquier, B

“…The Electrostatic Discharge (ESD) protection for advanced CMOS technologies is a challenge due to the technology scaling down. The main purpose of this paper…”
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In-situ heater for thermal assist recovery of MOS devices in 28 nm UTBB FD-SOI CMOS technology by Galy, P., Lethiecq, R., Bawedin, M.

“…Preliminary results are reported on an in-situ heater for thermal assist recovery of MOS transistor and is demonstrated in 28 nm Fully Depleted…”
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Capacitance RF Characterization and Modeling of 28 FD-SOI CMOS Transistors down to Cryogenic Temperature by Berlingard, Q., Lugo-Alvarez, J., Bawedin, M., Mota-Frutuoso, T., Durand, C., Gloria, D., Galy, P., Casse, M.

“…In this study we investigate the capacitance characterization and modeling of CMOS transistors integrated in 28nm Ultra Thin Body and Box (UTBB) Fully Depleted…”
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Extended investigation of a novel MOS device for in-situ heating in 28 nm UTBB FD-SOI CMOS technology by Lethiecq, R., Bawedin, M., Galy, P.

“…This work aims to present an extended investigation of a new N-MOS device designed in 28 nm FD-SOIUTBB high-k metal gate technology for in-situ heating…”
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FDSOI for cryoCMOS electronics: device characterization towards compact model by Casse, M., Paz, B. Cardoso, Bergamaschi, F., Ghibaudo, G., Serra, F., Billiot, G., Jansen, A. G. M., Berlingard, Q., Martinie, S., Bedecarrats, T., Contamin, L., Juge, A., Vincent, E., Galy, P., Pavanello, M.A, Vinet, M., Meunier, T., Gaillard, F.

“…We present a status of FDSOI transistors electrical characterization for very low temperature operation. We highlight in particular singular transport and…”
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Improved Retention Characteristics of Z 2 -FET Employing Half Back-Gate Control by Kwon, S., Navarro, C., Gamiz, F., Galy, P., Cristoloveanu, S., Kim, Y. -T., Ahn, J.

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