Search Results - "Fuketa, H."

Angular Dependency of Neutron-Induced Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM by Harada, R., Abe, S., Fuketa, H., Uemura, T., Hashimoto, M., Watanabe, Y.

“…This paper reports neutron-induced MCU (Multiple Cell Upset) measured in 0.4-V 65-nm 10T SRAM at two incident angles of 0 ° and 60 ° . The measurement results…”
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Milli-Kelvin Analysis Revealing the Role of Band-edge States in Cryogenic MOSFETs by Oka, H., Asai, H., Inaba, T., Shitakata, S., Yui, H., Fuketa, H., Iizuka, S., Kato, K., Nakayama, T., Mori, T.

“…We experimentally performed temperature-dependent current‒voltage (I‒V) analysis of Si n-MOSFETs down to 15 mK, for the first time. We found that the saturated…”
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Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits by Fuketa, H., Hashimoto, M., Mitsuyama, Y., Onoye, T.

“…We present an adaptive technique for compensating manufacturing and environmental variability in subthreshold circuits using "canary flip-flop (FF)," which can…”
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Insole Pedometer With Piezoelectric Energy Harvester and 2 V Organic Circuits by Ishida, K., Tsung-Ching Huang, Honda, K., Shinozuka, Y., Fuketa, H., Yokota, T., Zschieschang, U., Klauk, H., Tortissier, G., Sekitani, T., Toshiyoshi, H., Takamiya, M., Someya, T., Sakurai, T.

“…A shoe insole pedometer, which consists of a piezoelectric energy harvester and a 2 V organic pedometer circuit, has been developed as a first step toward the…”
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Demonstrating performance improvement of complementary TFET circuits by Ion enhancement based on isoelectronic trap technology by Mori, T., Asai, H., Hattori, J., Fukuda, K., Otsuka, S., Morita, Y., O'uchi, S., Fuketa, H., Migita, S., Mizubayashi, W., Ota, H., Matsukawa, T.

“…We improved the performance of a complementary circuit comprising Si-based tunnel field-effect transistors (TFETs) by using isoelectronic trap (IET)…”
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Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM by Fuketa, H., Hashimoto, M., Mitsuyama, Y., Onoye, T.

“…In this paper, the soft error rate (SER) induced by neutrons in 65-nm 10T static random access memory (SRAM) is measured over a wide range of supply voltages…”
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On-Chip Measurement System for Within-Die Delay Variation of Individual Standard Cells in 65-nm CMOS by Xin Zhang, Ishida, K., Fuketa, H., Takamiya, M., Sakurai, T.

“…New measurement system for characterizing within-die delay variations of individual standard cells is presented. The proposed measurement system are able to…”
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Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: V-Aware Dual Supply Voltage Technique by Fuketa, H., Hirairi, K., Yasufuku, T., Takamiya, M., Nomura, M., Shinohara, H., Sakurai, T.

“…To achieve the most energy-efficient operation, this brief presents a circuit design technique for separating the power supply voltage (V DD ) of flip-flops…”
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Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37V 980kHz near-threshold logic circuits by Fuketa, H., Nomura, M., Takamiya, M., Sakurai, T.

“…In order to improve the energy efficiency of logic circuits, reductions in capacitance (C) and power supply voltage (V DD ) are required, as energy consumption…”
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An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion by Fuketa, H, Kuroda, D, Hashimoto, M, Onoye, T

“…A self-timed subthreshold processor was developed in 65-nm complimentary metal-oxide-semiconductor process. This four-stage reduced instruction set computer…”
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13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO by Hirairi, K., Okuma, Y., Fuketa, H., Yasufuku, T., Takamiya, M., Nomura, M., Shinohara, H., Sakurai, T.

“…Scaling power supply voltages (V DD 's) of logic circuits down to the sub/near-threshold region is a promising approach to achieve significant power…”
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Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature by Takahashi, R., Takata, H., Yasufuku, T., Fuketa, H., Takamiya, M., Nomura, M., Shinohara, H., Sakurai, T.

“…Temperature dependence of 256 within-die random gate delay variations in sub-threshold logic circuits is measured in 40-nm CMOS test chips. When the…”
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Adaptive performance compensation with on-chip variation monitoring by Hashimoto, M., Fuketa, H.

“…This paper discusses adaptive performance control with two types of on-chip variation sensors. The first sensor aims to extract several device-parameters for…”
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Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits by Fuketa, H., Hashimoto, M., Mitsuyama, Y., Onoye, T.

“…This paper presents an adaptive technique for compensating manufacturing and environmental variability in subthreshold circuits using ldquocanary…”
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Differential Detection of MSK with Nonredundant Error Correction by Masamura, T., Samejima, S., Morihiro, Y., Fuketa, H.

“…A proposed scheme for differential detection of MSK with nonredundant error correction utilizes the output detected from the difference in phase between…”
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Alpha-particle-induced soft errors and multiple cell upsets in 65-nm 10T subthreshold SRAM by Fuketa, H, Hashimoto, M, Mitsuyama, Y, Onoye, T

“…This paper presents measurement results of alpha-particle-induced soft errors and multiple cell upsets (MCUs) in 65-nm 10 T SRAM with a wide range of supply…”
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1µm-thickness 64-channel surface electromyogram measurement sheet with 2V organic transistors for prosthetic hand control by Fuketa, H., Yoshioka, K., Shinozuka, Y., Ishida, K., Yokota, T., Matsuhisa, N., Inoue, Y., Sekino, M., Sekitani, T., Takamiya, M., Someya, T., Sakurai, T.

“…A surface electromyogram (EMG), which measures a voltage waveform produced by skeletal muscles on skin, is an important tool for applications detecting the…”
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A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates by Fuketa, Hiroshi, Iida, Satoshi, Yasufuku, Tadashi, Takamiya, Makoto, Nomura, Masahiro, Shinohara, Hirofumi, Sakurai, Takayasu

“…In this paper, a closed-form expression for estimating a minimum operating voltage (VDDmin) of CMOS logic gates is proposed. VDDmin is defined as the minimum…”
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Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits by Fuketa, H., Takahashi, R., Takamiya, M., Nomura, M., Shinohara, H., Sakurai, T.

“…Abnormal increase of the crosstalk noise in the sub-threshold logic circuits is found for the first time. When the threshold voltages (V TH ) of nMOS and pMOS…”
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K-Band Mobile Earth Station for Domestic Satellite Communications System by Egami, S., Okamoto, T., Fuketa, H.

“…Design considerations of a K -band (30/20 GHz) mobile earth station for a domestic satellite communications system are described. A Japanese Medium Capacity…”
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