Search Results - "Fukaishi, Muneo"

A 0.7-3GHz envelope ΔΣ modulator using phase modulated carrier clock for multi-mode/band switching amplifiers by Hori, S., Kunihiro, K., Takahashi, K., Fukaishi, M.

“…A 1-bit RF modulator using phase-modulated-carrier-clocking envelope ΔΣ modulation for a multi-mode/band transmitter is presented. The prototype IC designed in…”
Get full text

Introduction to the Special Section on the 2010 Asian Solid-State Circuits Conference (A-SSCC2010) by Fukuma, Masao, Fukaishi, Muneo

“…The 15 papers in this special section were originally presented at the 2010 Asian Solid-State Circuits Conference (A-SSCC2010), held in Beijing, China, from…”
Get full text

A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter by Tokairin, T, Okada, M, Kitsunezuka, M, Maeda, T, Fukaishi, M

“…A 2.1-to-2.8-GHz low-power consumption all-digital phase locked loop (ADPLL) with a time-windowed time-to-digital converter (TDC) is presented. The…”
Get full text

A Low-IF/Zero-IF Reconfigurable Analog Baseband IC With an I/Q Imbalance Cancellation Scheme by Kitsunezuka, Masaki, Tokairin, Takashi, Maeda, Tadashi, Fukaishi, Muneo

“…A low-IF/zero-IF reconfigurable analog baseband IC embodying an automatic I/Q imbalance cancellation scheme is reported. The chip, which comprises a…”
Get full text

A 30-MHz-2.4-GHz CMOS Receiver With Integrated RF Filter and Dynamic-Range-Scalable Energy Detector for Cognitive Radio Systems by Kitsunezuka, M., Kodama, H., Oshima, N., Kunihiro, K., Maeda, T., Fukaishi, M.

“…A 30-MHz-2.4-GHz complementary metal oxide semiconductor (CMOS) receiver with an integrated tunable RF filter and a dynamic-range-scalable energy detector for…”
Get full text

A 60 GHz Power Amplifier With 14.5 dBm Saturation Power and 25% Peak PAE in CMOS 65 nm SOI by Siligaris, Alexandre, Hamada, Yasuhiro, Mounet, Christopher, Raynaud, Christine, Martineau, Baudouin, Deparis, Nicolas, Rolland, Nathalie, Fukaishi, Muneo, Vincent, Pierre

“…A 60 GHz wideband power amplifier (PA) is fabricated in a standard CMOS SOI 65 nm process. The PA is based on two cascode stages. Input, output and inter-stage…”
Get full text

A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link by Miura, N., Mizoguchi, D., Inoue, M., Niitsu, K., Nakagawa, Y., Tago, M., Fukaishi, M., Sakurai, T., Kuroda, T.

“…A 1 Tb/s 3 W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1 GHz and data rate of 1 Gb/s per channel. 1024 data…”
Get full text

A 0.13-μm CMOS 5-Gb/s 10-m 28AWG cable transceiver with no-feedback-loop continuous-time post-equalizer by Yoshiharu Kudoh, Fukaishi, M., Mizuno, M.

“…The frequency-dependent attenuation of the transmission lines between chips and printed circuit boards, for example, is an obstacle to improving the…”
Get full text

Real-time current-waveform sensor with plugless energy harvesting from AC power lines for home/building energy-management systems by Takahashi, S, Yoshida, N, Maruhashi, K, Fukaishi, M

“…Home/building energy-management systems (EMSs) driven by information technology are expected to be key to the achievement of an upgraded energy infrastructure,…”
Get full text

Multi-GB/s Transceivers by Payne, Robert, Fukaishi, Muneo

“…Once isolated to optical communication systems, multi-Gb/s serial transceiver technology continues to be deployed in broader applications. The capability to…”
Get full text

A 0.3 - 3GHz reconfigurable digital transmitter with multi-bit envelope ΔΣ modulator using phase modulated carrier clock for wireless sensor networks by Hori, S., Kunihiro, K., Hayakawa, M., Fukaishi, M.

“…A reconfigurable digital transmitter for wireless sensors using phase-modulated-carrier-clocking multi-bit envelope ΔΣ modulation is presented. The prototype…”
Get full text

A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC by Tokairin, T., Okada, M., Kitsunezuka, M., Maeda, T., Fukaishi, M.

“…A 2.1-to-2.8 GHz low-power all-digital PLL with a time-windowed single-shot pulse-controlling 2-step TDC is presented. The test-chip is implemented in 90 nm…”
Get full text

A 30MHz-2.4GHz CMOS receiver with integrated RF filter and dynamic-range-scalable energy detector for cognitive radio by Kitsunezuka, M., Kodama, H., Oshima, N., Kunihiro, K., Maeda, T., Fukaishi, M.

“…A 30MHz-2.4GHz CMOS receiver with a highly linear integrated tunable RF filter, as well as with a dynamic-range-scalable RSSI-based energy detector for both…”
Get full text

A 60GHz power amplifier with 14.5dBm saturation power and 25% peak PAE in CMOS 65nm SOI by Siligaris, A., Hamada, Y., Mounet, C., Raynaud, C., Martineau, B., Deparis, N., Rolland, N., Fukaishi, M., Vincent, P.

“…A 60 GHz wideband power amplifier (PA) is fabricated in standard CMOS SOI 65 nm process. The PA is constituted by two cascode stages. Input, output and…”
Get full text

A 2.5-GHz four-phase clock generator with scalable no-feedback-loop architecture by Yamaguchi, K., Fukaishi, M., Sakamoto, T., Akiyama, N., Nakamura, K.

“…An accurate yet simple multiphase clock generator has been developed by using a delay compensation technique based on phase interpolation that supplies a…”
Get full text

A 20-Gb/s CMOS multichannel transmitter and receiver chip set for ultra-high-resolution digital displays by Fukaishi, M., Nakamura, K., Heiuchi, H., Hirota, Y., Nakazawa, Y., Ikeno, H., Hayama, H., Yotsuyanagi, M.

“…A multichannel transmitter (TX) and receiver (RX) chip set operating at 20 Gb/s (5 Gb/s/spl times/4 ch) has been developed by using 0.25-/spl mu/m CMOS…”
Get full text

A 4.25-Gb/s CMOS fiber channel transceiver with asynchronous tree-type demultiplexer and frequency conversion architecture by Fukaishi, M., Nakamura, K., Sato, M., Tsutsui, Y., Kishi, S., Yotsuyanagi, M.

“…A single-chip 1.25-Gb/s 32:1, 1:32 transceiver, as specified in the emerging American National Standards Institute fiber channel standard, has been developed…”
Get full text

A 100 Gb/s transceiver with GND-VDD common-mode receiver and flexible multi-channel aligner by Tanaka, Kenichi, Fukaishi, Muneo, Takeuchi, Masahiro, Yoshida, Nobuhide, Minami, Kouichirou, Yamaguchi, Kouichi, Uchida, Hiroyuki, Morishita, Yasuyuki, Sakamoto, Takehiko, Kaneko, Tomoyuki, Soda, Masaaki, Kurisu, Masakazu, Saeki, Takanori

“…A 5 Gb/s 20-channel transceiver uses 0.13 mu m 1.5 V CMOS technology. The sampling amplifier recovers plus or minus 100 mV 90 ps data over 0-1.5 V com-mon-mode…”
Get full text

0.1- mu m p super(+)-GaAs gate HJFET's fabricated using two-step dry-etching and selective MOMBE growth techniques by Wada, Shigeki, Furuhata, Naoki, Tokushima, Masatoshi, Fukaishi, Muneo, Hida, Hikaru, Maeda, Tadashi

“…This paper reports the first successful fabrication of high-performance, 0.1- mu m p super(+)-gate pseudomorphic heterojunction-FET's (HJFET's). By introducing…”
Get full text

A 2.125-Gb/s BiCMOS fiber channel transmitter for serial data communications by Fukaishi, M., Nakamura, S., Tajima, A., Kinoshita, Y., Suemura, Y., Suzuki, H., Itani, T., Miyamoto, H., Henmi, N., Yamazaki, T., Yotsuyanagi, M.

“…A 2.125-Gb/s transmitter meeting the specifications of the emerging ANSI Fiber Channel standard has been developed using BiCMOS technology. This transmitter…”
Get full text