Search Results - "Fu-Lung Hsueh"

A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network by Feng-Wei Kuo, Binsfeld Ferreira, Sandro, Huan-Neng Ron Chen, Lan-Chou Cho, Chewn-Pu Jou, Fu-Lung Hsueh, Madadi, Iman, Tohidian, Massoud, Shahmohammadi, Mina, Babaie, Masoud, Bogdan Staszewski, Robert

“…We present an ultra-low-power Bluetooth low-energy (BLE) transceiver (TRX) for the Internet of Things (IoT) optimized for digital 28-nm CMOS. A transmitter…”
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A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm by Babaie, Masoud, Feng-Wei Kuo, Huan-Neng Ron Chen, Lan-Chou Cho, Chewn-Pu Jou, Fu-Lung Hsueh, Shahmohammadi, Mina, Staszewski, Robert Bogdan

“…We propose a new transmitter architecture for ultra-low power radios in which the most energy-hungry RF circuits operate at a supply just above a threshold…”
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An On-Chip Electromagnetic Bandgap Structure with ESD Protection for Noise Suppression in 16-nm FinFET CMOS by Ming-Hsien Tsai, Sen-Kuei Hsu, Liu, Sally, Fu-Lung Hsueh

“…By using periodical electromagnetic bandgap (EBG) structure, a wideband band-stop filter (BSF) with ESD protection is first realized in 16-nm FinFET CMOS…”
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A Wideband Low Noise Amplifier With 4 kV HBM ESD Protection in 65 nm RF CMOS by Ming-Hsien Tsai, Hsu, S.S.H., Fu-Lung Hsueh, Chewn-Pu Jou, Sean Chen, Ming-Hsiang Song

“…This study presents a wideband low noise amplifier (LNA) including electrostatic discharge (ESD) protection circuits using 65 nm CMOS with a gate oxide…”
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A 17.5-26 GHz Low-Noise Amplifier With Over 8 kV ESD Protection in 65 nm CMOS by Ming-Hsien Tsai, Hsu, S. S. H., Fu-Lung Hsueh, Chewn-Pu Jou, Tzu-Jin Yeh

“…By the electrostatic discharge (ESD)/matching co-design methodology, a wideband low-noise amplifier (LNA) using a grounded spiral inductor in conjunction with…”
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Design of 60-GHz Low-Noise Amplifiers With Low NF and Robust ESD Protection in 65-nm CMOS by Ming-Hsien Tsai, Hsu, S. S. H., Fu-Lung Hsueh, Chewn-Pu Jou, Tzu-Jin Yeh

“…This paper presents two 60-GHz low-noise amplifiers (LNAs) with different electrostatic (ESD) protection schemes, including the diode-based and LC-based…”
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CMOS Image Sensor Random Telegraph Noise Time Constant Extraction From Correlated To Uncorrelated Double Sampling by Chao, Calvin Yi-Ping, Honyih Tu, Wu, Thomas, Kuo-Yu Chou, Shang-Fu Yeh, Fu-Lung Hsueh

“…A new method for on-chip random telegraph noise (RTN) characteristic time constant extraction using the double sampling circuit in an 8.3 Mpixel CMOS image…”
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ESD-Protected K-Band Low-Noise Amplifiers Using RF Junction Varactors in 65-nm CMOS by Ming-Hsien Tsai, Hsu, S. S. H., Fu-Lung Hsueh, Chewn-Pu Jou

“…This paper presents two K-band low-noise amplifiers (LNAs) in 65-nm CMOS using the proposed RF junction varactors as the ESD protection devices. The junction…”
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A Multi-ESD-Path Low-Noise Amplifier With a 4.3-A TLP Current Level in 65-nm CMOS by Ming-Hsien Tsai, Hsu, Shawn S H, Fu-Lung Hsueh, Chewn-Pu Jou

“…This paper studies the electrostatic discharge (ESD)-protected RF low-noise amplifiers (LNAs) in 65-nm CMOS technology. Three different ESD designs, including…”
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A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing by I-Ting Lee, Yen-Jen Chen, Shen-Iuan Liu, Chewn-Pu Jou, Fu-Lung Hsueh, Hsieh-Hung Hsieh

“…A low-phase-noise phase-locked loop (PLL) is widely used in clock generation, frequency synthesis, and data conversion. In a PLL using a sub-sampling phase…”
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A fully integrated 28nm Bluetooth Low-Energy transmitter with 36% system efficiency at 3dBm by Feng-Wei Kuo, Babaie, Masoud, Chen, Ron, Kyle Yen, Jinn-Yeh Chien, Lanchou Cho, Kuo, Fred, Chewn-Pu Jou, Fu-Lung Hsueh, Staszewski, Robert Bogdan

“…We propose a new transmitter (TX) architecture for ultra-low power radios. An all-digital PLL employs a digitally controlled oscillator with switching current…”
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A V-Band Divide-by-Three Injection-Locked Frequency Divider in 28 nm CMOS by HSIEH, Hsieh-Hung, LIU, Yi-Hsuan, YEH, Tzu-Jin, JOU, Chewn-Pu, HSUEH, Fu-Lung

“…In this letter, the 28 nm CMOS divide-by-three injection-locked frequency divider (ILFD) operating at the V band is presented for the first time. Based on a…”
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An Embedded Dynamic Voltage Scaling (DVS) System Through 55 nm Single-Inductor Dual-Output (SIDO) Switching Converter for 12-Bit Video Digital-to-Analog Converter by CHOU, Wen-Shen, HUANG, Tzu-Chi, HSU, Ying-Chih, PENG, Yung-Chow, HSUEH, Fu-Lung, LEE, Yu-Huei, YANG, Yao-Yi, SU, Yi-Ping, CHEN, Ke-Horng, HUANG, Chen-Chih, LIN, Ying-Hsi, LEE, Chao-Cheng, WEN, Kuei-Ann

“…This paper proposes a 55 nm CMOS 12-bit current-steering video digital-to-analog converter (DAC) directly powered by the single-inductor dual-output (SIDO)…”
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Extraction and Estimation of Pinned Photodiode Capacitance in CMOS Image Sensors by Chao, Calvin Yi-Ping, Yi-Che Chen, Kuo-Yu Chou, Jhy-Jyi Sze, Fu-Lung Hsueh, Shou-Gwo Wuu

“…The pinned photodiode capacitance extraction method proposed by Goiffon et al. is discussed, and two additional new methods are presented and analyzed; one…”
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Analog/RF wonderland: Circuit and technology co-optimization in advanced FinFET technology by Fu-Lung Hsueh, Yung-Chow Peng, Chung-Hui Chen, Tzu-Jin Yeh, Hsieh-Hung Hsieh, Chin-Ho Chang, Szu-Lin Liu, Mei-Chen Chuang, Chen, Mark

“…Stacked-gate is one of the most popular solutions used in mismatch-sensitive circuits in FinFET technology. A Bandgap circuit using stacked-gate formed by 150…”
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A 0.66erms− Temporal-Readout-Noise 3-D-Stacked CMOS Image Sensor With Conditional Correlated Multiple Sampling Technique by Shang-Fu Yeh, Kuo-Yu Chou, Hon-Yih Tu, Chao, Calvin Yi-Ping, Fu-Lung Hsueh

“…This paper presents a sub-electron temporal readout noise, 8.3 Mpixel and 1.1-μ pixel pitch 3-D-stacked CMOS image sensor (CIS). A conditional correlated…”
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A 53.6 GHz direct injection-locked frequency divider with a 72% locking range in 65 nm CMOS technology by Wen-Lin Chen, Shiao, Yu-Shao Jerry, Hsuan-Der Yen, Guo-Wei Huang, Hsieh-Hung Hsieh, Chewn-Pu Jou, Fu-Lung Hsueh

“…This study presents a 53.6 GHz wideband direct injection-locked frequency divider (DILFD) using 65 nm CMOS technology. By operating a RF input transistor in…”
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A V-band divide-by-three differential direct injection-locked frequency divider in 65-nm CMOS by Hsieh-Hung Hsieh, Fu-Lung Hsueh, Chewn-Pu Jou, Kuo, Fred, Chen, Sean, Tzu-Jin Yeh, Tan, Kevin Kai-Wen, Po-Yi Wu, Yu-Ling Lin, Ming-Hsien Tsai

“…In this paper, a novel circuit topology of CMOS divide-by-three injection-locked frequency divider is demonstrated. By using a differential direct injection…”
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A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology by Wei-Chih Chen, Chien-Chun Tsai, Chih-Hsien Chang, Yung-Chow Peng, Fu-Lung Hsueh, Tsung-Hsin Yu, Jinn-Yeh Chien, Wen-Hung Huang, Chi-Chang Lu, Mu-Shan Lin, Chin-Ming Fu, Shu-Chun Yang, Chung-Wing Wong, Wan-Te Chen, Chin-Hua Wen, Li Yueh Wang, Chiang Pu

“…This paper presents a 2.5-8Gb/s transceiver for PCI Express Gen3.0/2.0/1.0 applications. To overcome channel loss of high bit rate application, a linear…”
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A 6.5kV ESD-protected low noise amplifier in 65-nm CMOS by Ming-Hsien Tsai, Fu-Lung Hsueh, Chewn-Pu Jou, Ming-Hsiang Song, Jen-Chou Tseng, Hsu, Shawn S H, Sean Chen

“…A new ESD topology is proposed for RF low-noise amplifier (LNA). By using the modified silicon-controlled rectifier (MSCR) in conjunction with a P + /N-well…”
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