Search Results - "Fritzinger, L."

Reverse L-shape sealed poly-buffer LOCOS technology by Sung, J.M., Lu, C.Y., Fritzinger, L.B., Sheng, T.T., Lee, K.H.

“…A description is presented of a new LOCOS (local oxidation of silicon) isolation process, reverse-L-shaped sealed poly-buffer LOCOS (RLS-PBL), which can…”
Get full text

A folded extended window MOSFET for ULSI applications by Lu, C.-Y., Yaney, D.S., Lee, K.H., Twiford, M.S., Tsai, N.-S., Kook, T., Fritzinger, L.B., Chen, M.-L., Yang, T.S.

“…A novel, simple, and straightforward technology, FEWMNOS, for a high-packing-density LDD CMOS device, is described. A salicide polysilicon layer, termed a…”
Get full text

COM2 SiGe modular BiCMOS technology for digital, mixed-signal, and RF applications by Carroll, M., Ivanov, T., Kuehne, S., Chu, J., King, C., Frei, M., Mastrapasqua, M., Johnson, R., Ng, K., Moinian, S., Martin, S., Huang, C., Hsu, T., Nguyen, D., Singh, R., Fritzinger, L., Esry, T., Moller, W., Kane, B., Abeln, G., Hwang, D., Orphee, D., Lytle, S., Roby, M., Vitkavage, D., Chesire, D., Ashton, R., Shuttleworth, D., Thoma, M., Choi, S., Lewllen, S., Mason, P., Lai, T., Hsieh, H., Dennis, D., Harris, E., Thomas, S., Gregor, R., Sana, P., Wu, W.

“…The COM2 SiGe modular BiCMOS technology has been developed to allow efficient design and manufacturing of digital, mixed-signal, and RF integrated circuits, as…”
Get full text

Integration of poly buffered LOCOS and gate processing for submicrometer isolation technique by Juengling, W., Hillenius, S.J., Chen, M.L., Fritzinger, L.B.

“…A modified poly buffered LOCOS (PBL) process is described which simplifies processing and provides advantages over conventional PBL and LOCOS processes. The…”
Get full text

A low-cost modular SiGe BiCMOS technology and analog passives for high-performance RF and wide-band applications by Tang, R., Leung, C., Nguyen, D., Hsu, T., Fritzinger, L., Molloy, S., Esry, T., Ivanov, T., Chu, J., Carroll, M., Huang, J., Moller, W., Campbell, T., Cochran, W., King, C., Frei, M., Mastrapasqua, M., Ng, K., Chen, C., Johnson, R., Pullela, R., Archer, V., Krska, J., Moinian, S., Cong, H.

“…We present a low-cost 0.25 /spl mu/m SiGe BiCMOS technology that is being manufactured in an 8-inch production line. The technology includes modules for…”
Get full text

An Integrated Isolation/Gate Process For Sub-quarter Micron Technologies by Kangar, Hillenius, Baker, Nakahara, Chang, Chong-Cheng Fu, Fritzinger, Giniecki

“…We have demonstrated the feasibility of a novel process in which the oxide/poly stack used in poly buffer LOCOS (PBL) is the same as the oxide/poly of the…”
Get full text

25 /spl Aring/ gate oxide without boron penetration for 0.25 and 0.3-/spl mu/m PMOSFETs by Liu, C.T., Ma, Y., Cheung, K.P., Chang, C.P., Fritzinger, L., Becerro, J., Luftman, H., Vaidya, H.M., Colonell, J.I., Kamgar, A., Minor, J.F., Murray, R.G., Lai, W.Y.C., Pai, C.S., Hillenius, S.J.

“…Very thin gate oxides are necessary for small CMOS transistors. However, one major challenge is boron penetration through the thin gate oxides in…”
Get full text