Search Results - "Fleischer, Bruce"

DLFloat: A 16-b Floating Point Format Designed for Deep Learning Training and Inference by Agrawal, Ankur, Mueller, Silvia M., Fleischer, Bruce M., Sun, Xiao, Wang, Naigang, Choi, Jungwook, Gopalakrishnan, Kailash

“…The resilience of Deep Learning (DL) training and inference workloads to low-precision computations, coupled with the demand for power-and area-efficient…”
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Efficient AI System Design With Cross-Layer Approximate Computing by Venkataramani, Swagath, Sun, Xiao, Wang, Naigang, Chen, Chia-Yu, Choi, Jungwook, Kang, Mingu, Agarwal, Ankur, Oh, Jinwook, Jain, Shubham, Babinsky, Tina, Cao, Nianzheng, Fox, Thomas, Fleischer, Bruce, Gristede, George, Guillorn, Michael, Haynie, Howard, Inoue, Hiroshi, Ishizaki, Kazuaki, Klaiber, Michael, Lo, Shih-Hsien, Maier, Gary, Mueller, Silvia, Scheuermann, Michael, Ogawa, Eri, Schaal, Marcel, Serrano, Mauricio, Silberman, Joel, Vezyrtzis, Christos, Wang, Wei, Yee, Fanchieh, Zhang, Jintao, Ziegler, Matthew, Zhou, Ching, Ohara, Moriyoshi, Lu, Pong-Fei, Curran, Brian, Shukla, Sunil, Srinivasan, Vijayalakshmi, Chang, Leland, Gopalakrishnan, Kailash

“…Advances in deep neural networks (DNNs) and the availability of massive real-world data have enabled superhuman levels of accuracy on many AI tasks and ushered…”
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A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling by Lee, Sae Kyu, Agrawal, Ankur, Silberman, Joel, Ziegler, Matthew, Kang, Mingu, Venkataramani, Swagath, Cao, Nianzheng, Fleischer, Bruce, Guillorn, Michael, Cohen, Matthew, Mueller, Silvia M., Oh, Jinwook, Lutz, Martin, Jung, Jinwook, Koswatta, Siyu, Zhou, Ching, Zalani, Vidhi, Kar, Monodeep, Bonanno, James, Casatuta, Robert, Chen, Chia-Yu, Choi, Jungwook, Haynie, Howard, Herbert, Alyssa, Jain, Radhika, Kim, Kyu-Hyoun, Li, Yulong, Ren, Zhibin, Rider, Scot, Schaal, Marcel, Schelm, Kerstin, Scheuermann, Michael R., Sun, Xiao, Tran, Hung, Wang, Naigang, Wang, Wei, Zhang, Xin, Shah, Vinay, Curran, Brian, Srinivasan, Vijayalakshmi, Lu, Pong-Fei, Shukla, Sunil, Gopalakrishnan, Kailash, Chang, Leland

“…Reduced precision computation is a key enabling factor for energy-efficient acceleration of deep learning (DL) applications. This article presents a 7-nm…”
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Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC by Kar, Monodeep, Silberman, Joel, Venkataramani, Swagath, Srinivasan, Viji, Fleischer, Bruce, Rubin, Joshua, Lancaster, JohnDavid, Lee, Saekyu, Cohen, Matthew, Ziegler, Matthew, Cao, Nianzheng, Woodward, Sandra, Agrawal, Ankur, Zhou, Ching, Chatarasi, Prasanth, Gooding, Thomas, Guillorn, Michael, Hekmatshoartabari, Bahman, Jacob, Philip, Jain, Radhika, Jain, Shubham, Jung, Jinwook, Kim, Kyu-Hyoun, Koswatta, Siyu, Lutz, Martin, Mannari, Alberto, Mathew, Abey K., Nair, Indira, Ranjan, Ashish, Ren, Zhibin, Rider, Scot, Rower, Thomas, Satterfield, David, Schaal, Marcel, Sen, Sanchari, Tellez, Gustavo, Tran, Hung, Wang, Wei, Zalani, Vidhi, Zhang, Jintao, Zhang, Xin, Shah, Vinay, Senger, Robert, Kumar, Arvind, Lu, Pong-Fei, Chang, Leland

“…Discrete AI inference cards, operating under form-factor and system-defined peak power constraints, must serve diverse inference requests with widely varying…”
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RaPiD: AI Accelerator for Ultra-low Precision Training and Inference by Venkataramani, Swagath, Srinivasan, Vijayalakshmi, Wang, Wei, Sen, Sanchari, Zhang, Jintao, Agrawal, Ankur, Kar, Monodeep, Jain, Shubham, Mannari, Alberto, Tran, Hoang, Li, Yulong, Ogawa, Eri, Ishizaki, Kazuaki, Inoue, Hiroshi, Schaal, Marcel, Serrano, Mauricio, Choi, Jungwook, Sun, Xiao, Wang, Naigang, Chen, Chia-Yu, Allain, Allison, Bonano, James, Cao, Nianzheng, Casatuta, Robert, Cohen, Matthew, Fleischer, Bruce, Guillorn, Michael, Haynie, Howard, Jung, Jinwook, Kang, Mingu, Kim, Kyu-hyoun, Koswatta, Siyu, Lee, Saekyu, Lutz, Martin, Mueller, Silvia, Oh, Jinwook, Ranjan, Ashish, Ren, Zhibin, Rider, Scot, Schelm, Kerstin, Scheuermann, Michael, Silberman, Joel, Yang, Jie, Zalani, Vidhi, Zhang, Xin, Zhou, Ching, Ziegler, Matt, Shah, Vinay, Ohara, Moriyoshi, Lu, Pong-Fei, Curran, Brian, Shukla, Sunil, Chang, Leland, Gopalakrishnan, Kailash

“…The growing prevalence and computational demands of Artificial Intelligence (AI) workloads has led to widespread use of hardware accelerators in their…”
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14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC by Kar, Monodeep, Silberman, Joel, Venkataramani, Swagath, Srinivasan, Viji, Fleischer, Bruce, Rubin, Joshua, Lancaster, JohnDavid, Lee, Saekyu, Cohen, Matthew, Ziegler, Matthew, Cao, Nianzheng, Woodward, Sandra, Agrawal, Ankur, Zhou, Ching, Chatarasi, Prasanth, Gooding, Thomas, Guillorn, Michael, Hekmatshoartabari, Bahman, Jacob, Philip, Jain, Radhika, Jain, Shubham, Jung, Jinwook, Kim, Kyu-Hyoun, Koswatta, Siyu, Lutz, Martin, Mannari, Alberto, Mathew, Abey, Nair, Indira, Ranjan, Ashish, Ren, Zhibin, Rider, Scot, Roewer, Thomas, Satterfield, David, Schaal, Marcel, Sen, Sanchari, Tellez, Gustavo, Tran, Hung, Wang, Wei, Zalani, Vidhi, Zhang, Jintao, Zhang, Xin, Shah, Vinay, Senger, Robert, Kumar, Arvind, Lu, Pong-Fei, Chang, Leland

“…The rapid emergence of AI models, specifically large language models (LLMs) requiring large amounts of compute, drives the need for dedicated AI inference…”
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Low-Cost Concurrent Error Detection for Floating-Point Unit (FPU) Controllers by Maniatakos, M., Kudva, P., Fleischer, B. M., Makris, Y.

“…We present a nonintrusive concurrent error detection (CED) method for protecting the control logic of a contemporary floating-point unit (FPU). The proposed…”
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A Scalable Multi-TeraOPS Core for AI Training and Inference by Shukla, Sunil, Fleischer, Bruce, Ziegler, Matthew, Silberman, Joel, Oh, Jinwook, Srinivasan, Vijayalakshmi, Choi, Jungwook, Mueller, Silvia, Agrawal, Ankur, Babinsky, Tina, Cao, Nianzheng, Chen, Chia-Yu, Chuang, Pierce, Fox, Thomas, Gristede, George, Guillorn, Michael, Haynie, Howard, Klaiber, Michael, Lee, Dongsoo, Lo, Shih-Hsien, Maier, Gary, Scheuermann, Michael, Venkataramani, Swagath, Vezyrtzis, Christos, Wang, Naigang, Yee, Fanchieh, Zhou, Ching, Lu, Pong-Fei, Curran, Brian, Chang, Leland, Gopalakrishnan, Kailash

“…This letter presents a multi-TOPS AI accelerator core for deep learning training and inference. With a programmable architecture and custom ISA, this engine…”
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9.1 A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling by Agrawal, Ankur, Lee, Sae Kyu, Silberman, Joel, Ziegler, Matthew, Kang, Mingu, Venkataramani, Swagath, Cao, Nianzheng, Fleischer, Bruce, Guillorn, Michael, Cohen, Matthew, Mueller, Silvia, Oh, Jinwook, Lutz, Martin, Jung, Jinwook, Koswatta, Siyu, Zhou, Ching, Zalani, Vidhi, Bonanno, James, Casatuta, Robert, Chen, Chia-Yu, Choi, Jungwook, Haynie, Howard, Herbert, Alyssa, Jain, Radhika, Kar, Monodeep, Kim, Kyu-Hyoun, Li, Yulong, Ren, Zhibin, Rider, Scot, Schaal, Marcel, Schelm, Kerstin, Scheuermann, Michael, Sun, Xiao, Tran, Hung, Wang, Naigang, Wang, Wei, Zhang, Xin, Shah, Vinay, Curran, Brian, Srinivasan, Vijayalakshmi, Lu, Pong-Fei, Shukla, Sunil, Chang, Leland, Gopalakrishnan, Kailash

“…Low-precision computation is the key enabling factor to achieve high compute densities (TOPS/W and TOPS/mm 2 ) in AI hardware accelerators across cloud and…”
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A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference by Fleischer, Bruce, Shukla, Sunil, Ziegler, Matthew, Silberman, Joel, Jinwook Oh, Srinivasan, Vijavalakshmi, Jungwook Choi, Mueller, Silvia, Agrawal, Ankur, Babinsky, Tina, Nianzheng Cao, Chia-Yu Chen, Chuang, Pierce, Fox, Thomas, Gristede, George, Guillorn, Michael, Haynie, Howard, Klaiber, Michael, Dongsoo Lee, Shih-Hsien Lo, Maier, Gary, Scheuermann, Michael, Venkataramani, Swagath, Vezyrtzis, Christos, Naigang Wang, Fanchieh Yee, Ching Zhou, Pong-Fei Lu, Curran, Brian, Lel Chang, Gopalakrishnan, Kailash

“…A multi-TOPS AI core is presented for acceleration of deep learning training and inference in systems from edge devices to data centers. With a programmable…”
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Exponent monitoring for low-cost concurrent error detection in FPU control logic by Maniatakos, M, Makris, Y, Kudva, P, Fleischer, B

“…We present a non-intrusive concurrent error detection (CED) method for protecting the control logic of a contemporary floating point unit (FPU). The proposed…”
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A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation by Ditlow, G S, Montoye, R K, Storino, S N, Dance, S M, Ehrenreich, S, Fleischer, B M, Fox, T W, Holmes, K M, Mihara, J, Nakamura, Y, Onishi, S, Shearer, R, Wendel, D, Leland Chang

“…In multi-ported register files, memory cell size grows quadratically with the total number of ports due to wordline and bitline wiring. Reducing the number of…”
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Static timing analysis for self resetting circuits by Narayanan, Vinod, Chappell, Barbara A., Fleischer, Bruce M.

“…Static timing analysis techniques are widely used to verify the timing behavior of large digital designs implemented predominantly in conventional static CMOS…”
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64-bit prefix adders: Power-efficient topologies and design solutions by Ching Zhou, Fleischer, B.M., Gschwind, M., Puri, R.

“…64-bit adders of various prefix algorithms are designed using a novel dataflow synthesis methodology. Our synthesis methodology offers robust adder solutions…”
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A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference by Oh, Jinwook, Lee, Sae Kyu, Kang, Mingu, Ziegler, Matthew, Silberman, Joel, Agrawal, Ankur, Venkataramani, Swagath, Fleischer, Bruce, Guillorn, Michael, Choi, Jungwook, Wang, Wei, Mueller, Silvia, Ben-Yehuda, Shimon, Bonanno, James, Cao, Nianzheng, Casatuta, Robert, Chen, Chia-Yu, Cohen, Matt, Erez, Ophir, Fox, Thomas, Gristede, George, Haynie, Howard, Ivanov, Vicktoria, Koswatta, Siyu, Lo, Shih-Hsien, Lutz, Martin, Maier, Gary, Mesh, Alex, Nustov, Yevgeny, Rider, Scot, Schaal, Marcel, Scheuermann, Michael, Sun, Xiao, Wang, Naigang, Yee, Fanchieh, Zhou, Ching, Shah, Vinay, Curran, Brian, Srinivasan, Vijayalakshmi, Lu, Pong-Fei, Shukla, Sunil, Gopalakrishnan, Kailash, Chang, Leland

“…A processor core is presented for AI training and inference products. Leading-edge compute efficiency is achieved for robust fp16 training via efficient…”
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A statistical critical path monitor in 14nm CMOS by Fleischer, Bruce, Vezyrtzis, Christos, Balakrishnan, Karthik, Jenkins, Keith A.

“…Local variation of delay paths has a significant impact on modern microprocessor performance and yield. A critical path monitor is reported which extracts…”
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A 5GHz+ 128-bit Binary Floating-Point Adder for the POWER6 Processor by Xiao Yan Yu, Yiu-Hing Chan, Curran, B., Schwarz, E., Kelly, M., Fleischer, B.

“…A fast 128-bit end-around carry adder is designed and fabricated as part of the POWER6 floating-point unit in a 65nm SOI process technology. Efficient use of…”
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Synthesis design strategies for energy-efficient microprocessors by Ching Zhou, Yu-Shiang Lin, Pong-Fei Lu, Fleischer, Bruce M., Frank, David J., Chang, Leland

“…A detailed synthesis study has been performed on a functional unit from a recent IBM microprocessor to explore the voltage-frequency space for energy-efficient…”
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Jitter in relaxation oscillators by Fleischer, Bruce Martin

“…Relaxation oscillators can be used as modulators in information-transmission systems. Even with a fixed controlling input, however, a relaxation oscillator's…”
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Bruce Fleisher's Swing Keys : Stay down through the shot by Fleischer, Bruce

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