Data-driven logic synthesizer for acceleration of Forward propagation in artificial neural networks

We present a tool for automatically generating efficient feed-forward logic for hardware acceleration of artificial neural networks (ANNs). It produces circuitry in the form of synthesizable Verilog code that is optimized based on analyzing training data to minimize the numbers of bits in weights an...

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Bibliographic Details
Published in:	2015 33rd IEEE International Conference on Computer Design (ICCD) pp. 435 - 438
Main Authors:	Mahmoud, Khaled Z., Smith, William E., Fishkin, Mark, Miller, Timothy N.
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01-10-2015
Subjects:	Acceleration Artificial neural networks Entropy Hardware Optimization Topology Training
Online Access:	Get full text
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Summary:	We present a tool for automatically generating efficient feed-forward logic for hardware acceleration of artificial neural networks (ANNs). It produces circuitry in the form of synthesizable Verilog code that is optimized based on analyzing training data to minimize the numbers of bits in weights and values, thereby minimizing the number of logic gates in ANN components such as adders and multipliers. For an optimized ANN, different implementation topologies can be generated, including fully pipelined and simple state machines. Additional insights about hardware acceleration for neural networks are also presented. We show the impact of reducing precision relative to floating point and present area, power, delay, throughput, and energy estimates by circuit synthesis.
DOI:	10.1109/ICCD.2015.7357142