Radiation damage characterization of digital integrated circuits

A set of gates and registers was fabricated on a submicron CMOS process using radiation hardening by design techniques. The circuits were irradiated in a tandem accelerator with 10 MeV protons on three different doses. Off-line characterization of devices was carried out. Measurements showed minimum...

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Bibliographic Details

Published in:	2009 10th Latin American Test Workshop pp. 1 - 5
Main Authors:	Sondon, S., Mandolesi, P., Julian, P., Palumbo, F., Alurralde, M., Filevich, A.
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01-03-2009
Subjects:	CMOS logic circuits CMOS process Digital integrated circuits Electric variables measurement Integrated circuit measurements Integrated circuit noise Logic gates Proton accelerators Radiation hardening Registers
Online Access:	Get full text
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